{"id":"https://openalex.org/W2555470558","doi":"https://doi.org/10.1109/is.2016.7737483","title":"Generalized net models of basic sequential logic circuits","display_name":"Generalized net models of basic sequential logic circuits","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2555470558","doi":"https://doi.org/10.1109/is.2016.7737483","mag":"2555470558"},"language":"en","primary_location":{"id":"doi:10.1109/is.2016.7737483","is_oa":false,"landing_page_url":"https://doi.org/10.1109/is.2016.7737483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 8th International Conference on Intelligent Systems (IS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007803228","display_name":"Lenko Erbakanov","orcid":null},"institutions":[{"id":"https://openalex.org/I4210108077","display_name":"Prof. Assen Zlatarov University","ror":"https://ror.org/020ak9w19","country_code":"BG","type":"education","lineage":["https://openalex.org/I4210108077"]}],"countries":["BG"],"is_corresponding":false,"raw_author_name":"Lenko Erbakanov","raw_affiliation_strings":["Intelligent Systems Laboratory, Prof. Asen Zlatarov University, Burgas, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Laboratory, Prof. Asen Zlatarov University, Burgas, Bulgaria","institution_ids":["https://openalex.org/I4210108077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038199341","display_name":"Krassimir Atanassov","orcid":"https://orcid.org/0000-0001-5625-071X"},"institutions":[{"id":"https://openalex.org/I4210108077","display_name":"Prof. Assen Zlatarov University","ror":"https://ror.org/020ak9w19","country_code":"BG","type":"education","lineage":["https://openalex.org/I4210108077"]}],"countries":["BG"],"is_corresponding":false,"raw_author_name":"Krassimir Atanassov","raw_affiliation_strings":["Intelligent Systems Laboratory, Prof. Asen Zlatarov University, Burgas, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Laboratory, Prof. Asen Zlatarov University, Burgas, Bulgaria","institution_ids":["https://openalex.org/I4210108077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019081739","display_name":"Sotir Sotirov","orcid":"https://orcid.org/0000-0003-1292-6225"},"institutions":[{"id":"https://openalex.org/I4210103918","display_name":"Institute of Biophysics and Biomedical Engineering","ror":"https://ror.org/01dxqkr82","country_code":"BG","type":"facility","lineage":["https://openalex.org/I24768866","https://openalex.org/I4210103918"]}],"countries":["BG"],"is_corresponding":false,"raw_author_name":"Sotir Sotirov","raw_affiliation_strings":["Institute of Biophysics and Biomedical Engineering, 105 \u201cAcad. G. Bonchev\u201d Str, Sofia, Bulgaria","Institute of Biophysics and Biomedical Engineering, 105 \"Acad. G. Bonchev\" Str, Sofia, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Biophysics and Biomedical Engineering, 105 \u201cAcad. G. Bonchev\u201d Str, Sofia, Bulgaria","institution_ids":["https://openalex.org/I4210103918"]},{"raw_affiliation_string":"Institute of Biophysics and Biomedical Engineering, 105 \"Acad. G. Bonchev\" Str, Sofia, Bulgaria","institution_ids":["https://openalex.org/I4210103918"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055648494","display_name":"Stanislav Simeonov","orcid":"https://orcid.org/0000-0002-8145-405X"},"institutions":[{"id":"https://openalex.org/I4210108077","display_name":"Prof. Assen Zlatarov University","ror":"https://ror.org/020ak9w19","country_code":"BG","type":"education","lineage":["https://openalex.org/I4210108077"]}],"countries":["BG"],"is_corresponding":false,"raw_author_name":"Stanislav Simeonov","raw_affiliation_strings":["Intelligent Systems Laboratory, Prof. Asen Zlatarov University, Burgas, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Systems Laboratory, Prof. Asen Zlatarov University, Burgas, Bulgaria","institution_ids":["https://openalex.org/I4210108077"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"579","last_page":"583"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14175","display_name":"Intuitionistic Fuzzy Systems Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14175","display_name":"Intuitionistic Fuzzy Systems Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10080","display_name":"Energy Efficient Wireless Sensor Networks","score":0.9189000129699707,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.7235956192016602},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6658463478088379},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.638536810874939},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5621833205223083},{"id":"https://openalex.org/keywords/continuation","display_name":"Continuation","score":0.556175947189331},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5387950539588928},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5113937258720398},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4567921459674835},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4493553638458252},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42325058579444885},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3898736238479614},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3811511993408203},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.28404200077056885},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2545732259750366},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1331700086593628},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09689053893089294},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09582898020744324}],"concepts":[{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.7235956192016602},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6658463478088379},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.638536810874939},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5621833205223083},{"id":"https://openalex.org/C88626702","wikidata":"https://www.wikidata.org/wiki/Q1128903","display_name":"Continuation","level":2,"score":0.556175947189331},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5387950539588928},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5113937258720398},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4567921459674835},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4493553638458252},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42325058579444885},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3898736238479614},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3811511993408203},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.28404200077056885},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2545732259750366},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1331700086593628},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09689053893089294},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09582898020744324},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/is.2016.7737483","is_oa":false,"landing_page_url":"https://doi.org/10.1109/is.2016.7737483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 8th International Conference on Intelligent Systems (IS)","raw_type":"proceedings-article"},{"id":"pmh:oai:bpos.bg:55690","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S7407055231","display_name":"Bulgarian Portal for Open Science","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"research article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1933503205","https://openalex.org/W2001236151","https://openalex.org/W2045460788","https://openalex.org/W2403759617","https://openalex.org/W2412550452","https://openalex.org/W2465171300","https://openalex.org/W2508750331","https://openalex.org/W2582806324","https://openalex.org/W4246222535"],"related_works":["https://openalex.org/W2746929098","https://openalex.org/W2386022279","https://openalex.org/W2113700423","https://openalex.org/W4296473373","https://openalex.org/W2108229542","https://openalex.org/W3148292035","https://openalex.org/W2542280163","https://openalex.org/W2362510906","https://openalex.org/W2059422871","https://openalex.org/W1966764473"],"abstract_inverted_index":{"This":[0],"paper":[1],"is":[2],"a":[3,38],"continuation":[4],"of":[5,16,18,40,60,82],"the":[6,19,33,75,79],"previous":[7],"two":[8,17],"papers":[9],"[7,":[10],"8],":[11],"representing":[12],"generalized":[13],"net":[14],"models":[15],"basic":[20],"sequential":[21],"logic":[22],"circuits":[23,43,56],"-":[24],"SR":[25],"and":[26,69],"JK":[27],"flip-flop":[28],"circuits.":[29],"We":[30],"can":[31,45,73],"perform":[32],"measurements,":[34],"if":[35],"we":[36,72],"have":[37],"set":[39],"several":[41,66],"logical":[42,55,62],"that":[44],"be":[46,58],"used":[47],"to":[48],"obtain":[49],"identical":[50],"output":[51],"data.":[52],"The":[53],"aforementioned":[54],"must":[57],"composed":[59],"different":[61,70],"elements.":[63],"By":[64],"using":[65],"measurement":[67],"points":[68],"schematics,":[71],"infer":[74],"best":[76],"solution":[77],"for":[78],"considered":[80],"type":[81],"task.":[83]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}