{"id":"https://openalex.org/W4396949200","doi":"https://doi.org/10.1109/irps48228.2024.10529398","title":"Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network","display_name":"Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network","publication_year":2024,"publication_date":"2024-04-14","ids":{"openalex":"https://openalex.org/W4396949200","doi":"https://doi.org/10.1109/irps48228.2024.10529398"},"language":"en","primary_location":{"id":"doi:10.1109/irps48228.2024.10529398","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/irps48228.2024.10529398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018572841","display_name":"Minki Cho","orcid":"https://orcid.org/0000-0003-3745-122X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Minki Cho","raw_affiliation_strings":["Quality and Reliability Test Chips Design &#x0026; Data Intel,Hillsboro,OR,USA"],"affiliations":[{"raw_affiliation_string":"Quality and Reliability Test Chips Design &#x0026; Data Intel,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082638823","display_name":"B. Gill","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Balkaran Gill","raw_affiliation_strings":["Quality and Reliability Test Chips Design &#x0026; Data Intel,Hillsboro,OR,USA"],"affiliations":[{"raw_affiliation_string":"Quality and Reliability Test Chips Design &#x0026; Data Intel,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041445236","display_name":"Rahul Sharma","orcid":"https://orcid.org/0009-0005-9037-2549"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rahul Sharma","raw_affiliation_strings":["Quality and Reliability Test Chips Design &#x0026; Data Intel,Bangalore,India"],"affiliations":[{"raw_affiliation_string":"Quality and Reliability Test Chips Design &#x0026; Data Intel,Bangalore,India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045933761","display_name":"Shiv Shankar Gupta","orcid":"https://orcid.org/0000-0002-9607-9301"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shiv Gupta","raw_affiliation_strings":["Quality and Reliability Test Chips Design &#x0026; Data Intel,Bangalore,India"],"affiliations":[{"raw_affiliation_string":"Quality and Reliability Test Chips Design &#x0026; Data Intel,Bangalore,India","institution_ids":["https://openalex.org/I4210146682"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5018572841"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.1955,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.44707698,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9053357839584351},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.810217022895813},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7121092081069946},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.608729898929596},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6050584316253662},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4989469051361084},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.47858595848083496},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.456747442483902},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4510280191898346},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3686596155166626},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3651893734931946},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20704805850982666},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17185372114181519},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09240353107452393},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07257658243179321}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9053357839584351},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.810217022895813},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7121092081069946},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.608729898929596},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6050584316253662},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4989469051361084},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.47858595848083496},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.456747442483902},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4510280191898346},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3686596155166626},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3651893734931946},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20704805850982666},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17185372114181519},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09240353107452393},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07257658243179321},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps48228.2024.10529398","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/irps48228.2024.10529398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7599999904632568,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2156476900","https://openalex.org/W2157486149","https://openalex.org/W2161537396","https://openalex.org/W2163095973","https://openalex.org/W2921886179","https://openalex.org/W4225320158"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W3006003651","https://openalex.org/W4386968318","https://openalex.org/W2040807843","https://openalex.org/W2088914741","https://openalex.org/W2294981364","https://openalex.org/W4247180033","https://openalex.org/W2137310043","https://openalex.org/W2337711143","https://openalex.org/W2495024767"],"abstract_inverted_index":{"Reliability":[0],"of":[1,21,27,38,60],"the":[2,8,14,25,28,36,46,56,61,71,103,112,129,133],"clock":[3,29,47,52,62,66,76,85,94,108,116],"signal":[4],"is":[5,19,68],"critical":[6],"for":[7,54,102,115],"digital":[9],"and":[10,49],"analog":[11],"system":[12],"in":[13,24,45],"nanometer":[15],"technology.":[16,74],"Duty":[17],"cycle":[18,43,81,99,121,131],"one":[20,88],"key":[22],"metric":[23],"performance":[26],"signal.":[30],"In":[31],"this":[32],"work,":[33],"we":[34],"explore":[35],"impact":[37],"wear":[39],"out":[40],"induced":[41],"duty":[42,80,98,120,130,135],"shift":[44,82],"network":[48,63],"propose":[50],"adaptive":[51,107],"gating":[53,67,77,86,95,109,117],"improving":[55],"reliability.":[57],"Aging":[58],"behavior":[59],"with":[64,70,87],"conventional":[65],"measured":[69],"tri-gate":[72],"CMOS":[73],"Conventional":[75],"shows":[78],"asymmetric":[79],"due":[83],"to":[84,127],"polarity.":[89],"This":[90],"paper":[91],"presents":[92],"various":[93],"scenarios":[96],"where":[97],"behaves":[100],"differently":[101],"lifetime.":[104],"The":[105,124],"proposed":[106],"approach":[110],"selects":[111],"optimal":[113],"polarity":[114],"by":[118],"monitoring":[119],"on":[122],"chip.":[123],"work":[125],"demonstrates":[126],"maintain":[128],"within":[132],"target":[134],"cycle.":[136]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
