{"id":"https://openalex.org/W3039428974","doi":"https://doi.org/10.1109/irps45951.2020.9129601","title":"Modeling Framework for Transistor Aging Playback in Advanced Technology Nodes","display_name":"Modeling Framework for Transistor Aging Playback in Advanced Technology Nodes","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3039428974","doi":"https://doi.org/10.1109/irps45951.2020.9129601","mag":"3039428974"},"language":"en","primary_location":{"id":"doi:10.1109/irps45951.2020.9129601","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps45951.2020.9129601","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058069344","display_name":"Inanc Meric","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"I. Meric","raw_affiliation_strings":["Logic Technology Development Quality and Reliability"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027832758","display_name":"S. Ramey","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Ramey","raw_affiliation_strings":["Logic Technology Development Quality and Reliability"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079033229","display_name":"S. Novak","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Novak","raw_affiliation_strings":["Logic Technology Development Quality and Reliability"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017300759","display_name":"Sarthak Gupta","orcid":"https://orcid.org/0000-0003-2498-2603"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Gupta","raw_affiliation_strings":["Pre-Silicon Quality and Reliability"],"affiliations":[{"raw_affiliation_string":"Pre-Silicon Quality and Reliability","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021149298","display_name":"S. Mudanai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. P. Mudanai","raw_affiliation_strings":["Logic Technology Development Advanced Design Intel Co, Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Advanced Design Intel Co, Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062266688","display_name":"J. Hicks","orcid":"https://orcid.org/0000-0002-7480-0719"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Hicks","raw_affiliation_strings":["Logic Technology Development Quality and Reliability"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5058069344"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.233,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.79266924,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8917149305343628},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8203813433647156},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7026655673980713},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6027020812034607},{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.5851601958274841},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5192508697509766},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5142368674278259},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.49602803587913513},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.4215683341026306},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.41096335649490356},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3458757996559143},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33031296730041504},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23811239004135132},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20054009556770325},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11114421486854553}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8917149305343628},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8203813433647156},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7026655673980713},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6027020812034607},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.5851601958274841},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5192508697509766},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5142368674278259},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.49602803587913513},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.4215683341026306},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.41096335649490356},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3458757996559143},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33031296730041504},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23811239004135132},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20054009556770325},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11114421486854553},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps45951.2020.9129601","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps45951.2020.9129601","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"display_name":"Responsible consumption and production","id":"https://metadata.un.org/sdg/12"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1584496665","https://openalex.org/W1966797259","https://openalex.org/W1982281828","https://openalex.org/W2026610840","https://openalex.org/W2028568402","https://openalex.org/W2144545104","https://openalex.org/W2167724032","https://openalex.org/W2540699116","https://openalex.org/W2540962972","https://openalex.org/W2786278916","https://openalex.org/W2787310733","https://openalex.org/W3005547375","https://openalex.org/W6748061881"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W1811213809","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2006330903","https://openalex.org/W1742453416"],"abstract_inverted_index":{"With":[0],"continuous":[1],"channel":[2],"length":[3],"scaling":[4],"and":[5,14,17,64,75,85,91,94],"ongoing":[6],"demand":[7],"for":[8,27,82],"higher":[9],"operating":[10],"frequencies,":[11],"HCI":[12,18,76],"degradation":[13],"combining":[15],"BTI":[16,74],"aging":[19,23,37],"mechanisms":[20],"in":[21],"compact":[22],"models":[24],"becomes":[25],"important":[26],"accurately":[28],"capturing":[29],"end-of-life":[30],"circuit":[31],"behavior.":[32],"We":[33],"have":[34],"developed":[35],"an":[36],"playback":[38],"model":[39,56],"that":[40],"can":[41,79],"replay":[42],"aged":[43],"transistor":[44,59],"I-V":[45],"characteristics":[46],"over":[47],"a":[48,65],"large":[49],"bias":[50],"range":[51],"including":[52],"both":[53,83],"mechanisms.":[54],"The":[55],"uses":[57],"the":[58,70],"VT":[60],"shift,":[61],"mobility":[62],"degradation,":[63],"localization":[66],"coefficient":[67],"to":[68],"combine":[69],"impact":[71],"of":[72,97],"individual":[73],"components.":[77],"It":[78],"be":[80],"used":[81],"NMOS":[84],"PMOS,":[86],"as":[87,89],"well":[88],"logic":[90],"I/O":[92],"devices":[93],"is":[95],"part":[96],"Intel":[98],"process":[99],"design":[100],"kits.":[101]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
