{"id":"https://openalex.org/W3039974217","doi":"https://doi.org/10.1109/irps45951.2020.9129277","title":"Silicon Reliability Characterization of Intel\u2019s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking","display_name":"Silicon Reliability Characterization of Intel\u2019s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3039974217","doi":"https://doi.org/10.1109/irps45951.2020.9129277","mag":"3039974217"},"language":"en","primary_location":{"id":"doi:10.1109/irps45951.2020.9129277","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps45951.2020.9129277","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085027810","display_name":"C. Prasad","orcid":"https://orcid.org/0000-0001-8786-5389"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chetan Prasad","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040559708","display_name":"Sunny Chugh","orcid":"https://orcid.org/0000-0002-3062-6157"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sunny Chugh","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009492801","display_name":"Hannes Greve","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hannes Greve","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027147034","display_name":"I-chen Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"I-chen Ho","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028656679","display_name":"Kabir Enamul","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Enamul Kabir","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079982824","display_name":"Che-Yun Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheyun Lin","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110603084","display_name":"M. A. Maksud","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mahjabin Maksud","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109465524","display_name":"Steven Novak","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven R. Novak","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087301820","display_name":"Benjamin Orr","orcid":"https://orcid.org/0000-0002-6744-3071"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benjamin Orr","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038511241","display_name":"Keun Woo Park","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Keun Woo Park","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033338465","display_name":"A. Schmitz","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anthony Schmitz","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101734731","display_name":"Zhizheng Zhang","orcid":"https://orcid.org/0000-0001-9851-6184"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhizheng Zhang","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development Quality and Reliability,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052210693","display_name":"Peng Bai","orcid":"https://orcid.org/0000-0002-4231-3756"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peng Bai","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039387792","display_name":"D. Ingerly","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Doug B. Ingerly","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Logic Technology Development,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Logic Technology Development,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036623403","display_name":"Emre Armagan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Emre Armagan","raw_affiliation_strings":["Assembly Test Technology Development Quality and Reliability, Intel Corporation, Chandler, AZ, U.S.A","Intel Corporation,Assembly Test Technology Development Quality and Reliability,Chandler,AZ,U.S.A"],"affiliations":[{"raw_affiliation_string":"Assembly Test Technology Development Quality and Reliability, Intel Corporation, Chandler, AZ, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Assembly Test Technology Development Quality and Reliability,Chandler,AZ,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102339540","display_name":"Hsinwei Wu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hsinwei Wu","raw_affiliation_strings":["Assembly Test Technology Development Quality and Reliability, Intel Corporation, Chandler, AZ, U.S.A","Intel Corporation,Assembly Test Technology Development Quality and Reliability,Chandler,AZ,U.S.A"],"affiliations":[{"raw_affiliation_string":"Assembly Test Technology Development Quality and Reliability, Intel Corporation, Chandler, AZ, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Assembly Test Technology Development Quality and Reliability,Chandler,AZ,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007271322","display_name":"Patrick Stover","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Patrick Stover","raw_affiliation_strings":["Assembly Test Technology Development, Intel Corporation, Chandler, AZ, U.S.A","Intel Corporation,Assembly Test Technology Development,Chandler,AZ,U.S.A"],"affiliations":[{"raw_affiliation_string":"Assembly Test Technology Development, Intel Corporation, Chandler, AZ, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Assembly Test Technology Development,Chandler,AZ,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087973065","display_name":"Lance C. Hibbeler","orcid":"https://orcid.org/0000-0001-9305-4419"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lance Hibbeler","raw_affiliation_strings":["Technology Computed Aided Design, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Technology Computed Aided Design,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Technology Computed Aided Design, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Technology Computed Aided Design,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015947913","display_name":"Michael O'Day","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michael O'Day","raw_affiliation_strings":["Intel Corporation,Technology Computed Aided Design,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Technology Computed Aided Design,Hillsboro,OR,U.S.A","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018502320","display_name":"Daniel Pantuso","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daniel Pantuso","raw_affiliation_strings":["Technology Computed Aided Design, Intel Corporation, Hillsboro, OR, U.S.A","Intel Corporation,Technology Computed Aided Design,Hillsboro,OR,U.S.A"],"affiliations":[{"raw_affiliation_string":"Technology Computed Aided Design, Intel Corporation, Hillsboro, OR, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation,Technology Computed Aided Design,Hillsboro,OR,U.S.A","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":20,"corresponding_author_ids":["https://openalex.org/A5085027810"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.1302,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.77798732,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11301","display_name":"Advanced Surface Polishing Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stacking","display_name":"Stacking","score":0.7754476070404053},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7400356531143188},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.57680344581604},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5554966926574707},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5465483665466309},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5411367416381836},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5391170978546143},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.5134523510932922},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.5072748064994812},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.49085551500320435},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4828813374042511},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.4705389142036438},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4435432255268097},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4313315451145172},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41408810019493103},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.39367613196372986},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3103930354118347},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2602418065071106},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.25353530049324036},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1995874047279358},{"id":"https://openalex.org/keywords/structural-engineering","display_name":"Structural engineering","score":0.13214293122291565},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.12591686844825745}],"concepts":[{"id":"https://openalex.org/C33347731","wikidata":"https://www.wikidata.org/wiki/Q285210","display_name":"Stacking","level":2,"score":0.7754476070404053},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7400356531143188},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.57680344581604},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5554966926574707},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5465483665466309},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5411367416381836},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5391170978546143},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.5134523510932922},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.5072748064994812},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.49085551500320435},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4828813374042511},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.4705389142036438},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4435432255268097},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4313315451145172},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41408810019493103},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.39367613196372986},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3103930354118347},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2602418065071106},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25353530049324036},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1995874047279358},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.13214293122291565},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.12591686844825745},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps45951.2020.9129277","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps45951.2020.9129277","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2020859763","https://openalex.org/W2096571799","https://openalex.org/W2104386725","https://openalex.org/W2786278916","https://openalex.org/W2800054291","https://openalex.org/W2970159066","https://openalex.org/W2970793955","https://openalex.org/W2970916899","https://openalex.org/W3005962614","https://openalex.org/W4230880112"],"related_works":["https://openalex.org/W2027159884","https://openalex.org/W1990828594","https://openalex.org/W2748443500","https://openalex.org/W2089377260","https://openalex.org/W2046139226","https://openalex.org/W2513353273","https://openalex.org/W2549021975","https://openalex.org/W2333804548","https://openalex.org/W1968957853","https://openalex.org/W2310189477"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"silicon":[3,72],"reliability":[4,42],"characterization":[5],"of":[6,34],"Intel\u2019s":[7],"Foveros":[8,63],"three-dimensional":[9],"(3D)":[10],"logic-on-logic":[11],"stacking":[12,65],"technology":[13,48,66],"implemented":[14],"on":[15,37,57],"the":[16,58],"22FFL":[17],"process":[18,61],"node.":[19],"Simulations":[20],"and":[21,40,51],"data":[22],"demonstrate":[23],"mechanical":[24],"strain":[25],"safe":[26],"zones":[27],"around":[28],"Through":[29],"Silicon":[30],"Vias":[31],"(TSVs).":[32],"Evaluations":[33],"TSV":[35,50],"impact":[36],"transistor,":[38],"interconnect,":[39],"defect":[41],"are":[43],"reported":[44],"with":[45],"a":[46],"Si":[47],"focus.":[49],"bump":[52],"architectures":[53],"pass":[54],"thermomechanical":[55],"assessments":[56],"final":[59],"optimized":[60],"flow.":[62],"3D":[64],"is":[67],"shown":[68],"to":[69],"exhibit":[70],"robust":[71],"reliability.":[73]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}