{"id":"https://openalex.org/W3039112961","doi":"https://doi.org/10.1109/irps45951.2020.9128314","title":"Reliability Characterization for 12 V Application Using the 22FFL FinFET Technology","display_name":"Reliability Characterization for 12 V Application Using the 22FFL FinFET Technology","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3039112961","doi":"https://doi.org/10.1109/irps45951.2020.9128314","mag":"3039112961"},"language":"en","primary_location":{"id":"doi:10.1109/irps45951.2020.9128314","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps45951.2020.9128314","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002170896","display_name":"Cheng\u2010Yong Su","orcid":"https://orcid.org/0000-0003-3604-7858"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":true,"raw_author_name":"C.-Y. Su","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049261167","display_name":"M Armstrong","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Armstrong","raw_affiliation_strings":["Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040559708","display_name":"Sunny Chugh","orcid":"https://orcid.org/0000-0002-3062-6157"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"S. Chugh","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076962976","display_name":"Mohamed El\u2010Tanani","orcid":"https://orcid.org/0000-0002-4735-5445"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. El-tanani","raw_affiliation_strings":["Device Development Group, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Device Development Group, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009492801","display_name":"Hannes Greve","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"H. Greve","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035225490","display_name":"Hai Li","orcid":"https://orcid.org/0000-0001-7668-569X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Li","raw_affiliation_strings":["Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110603084","display_name":"M. A. Maksud","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"M. Maksud","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087301820","display_name":"Benjamin Orr","orcid":"https://orcid.org/0000-0002-6744-3071"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"B. Orr","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066092054","display_name":"Christopher J. Perini","orcid":"https://orcid.org/0000-0001-5332-7187"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"C. Perini","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002734333","display_name":"J. Palmer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"J. Palmer","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021827651","display_name":"L. Paulson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Paulson","raw_affiliation_strings":["Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027832758","display_name":"S. Ramey","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Ramey","raw_affiliation_strings":["Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089764842","display_name":"James Waldemer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Waldemer","raw_affiliation_strings":["Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037772811","display_name":"Yong Yang","orcid":"https://orcid.org/0000-0003-3372-071X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Yang","raw_affiliation_strings":["Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Portland Technology Development Department, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033187578","display_name":"D. Young","orcid":"https://orcid.org/0000-0001-9912-2320"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210119464","display_name":"Quality and Reliability (Greece)","ror":"https://ror.org/02f8mda22","country_code":"GR","type":"company","lineage":["https://openalex.org/I4210119464"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"D. Young","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I4210119464","https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":15,"corresponding_author_ids":["https://openalex.org/A5002170896"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210119464"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0569211,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.8026508688926697},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.6915925145149231},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.49288177490234375},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48795217275619507},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4684489071369171},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46478769183158875},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4309844374656677},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41672319173812866},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3470584750175476},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31777021288871765},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.118588387966156}],"concepts":[{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.8026508688926697},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.6915925145149231},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.49288177490234375},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48795217275619507},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4684489071369171},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46478769183158875},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4309844374656677},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41672319173812866},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3470584750175476},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31777021288871765},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.118588387966156},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps45951.2020.9128314","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps45951.2020.9128314","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1521797722","https://openalex.org/W1972638602","https://openalex.org/W2024218430","https://openalex.org/W2114882541","https://openalex.org/W2121259504","https://openalex.org/W2156373378","https://openalex.org/W2162517322","https://openalex.org/W2742586988","https://openalex.org/W2786278916","https://openalex.org/W2800054291","https://openalex.org/W2914643564","https://openalex.org/W6748061881"],"related_works":["https://openalex.org/W2033512842","https://openalex.org/W4322734194","https://openalex.org/W4233600955","https://openalex.org/W2913665393","https://openalex.org/W2369695847","https://openalex.org/W3005535424","https://openalex.org/W2994319598","https://openalex.org/W2047067935","https://openalex.org/W1607054433","https://openalex.org/W2110842462"],"abstract_inverted_index":{"The":[0,49,72],"22FFL":[1],"technology":[2,19,36,77],"developed":[3],"for":[4],"operation":[5],"to":[6,10,17,21,44,85],"3.3V":[7],"is":[8,62,80],"used":[9],"investigate":[11],"process":[12],"and":[13,60,65],"design":[14,88],"considerations":[15],"required":[16],"extend":[18],"capability":[20,78],"12":[22],"V":[23],"applications.":[24],"A":[25],"prototype":[26],"chip":[27],"was":[28],"carefully":[29],"designed":[30],"in":[31],"close":[32],"consideration":[33],"with":[34,82],"the":[35,40],"reliability":[37,47,50],"requirements":[38],"of":[39,51],"lower":[41],"voltage":[42],"components":[43,52],"demonstrate":[45,74],"product-level":[46],"capabilities.":[48],"such":[53],"as":[54],"transistors,":[55],"well":[56],"junctions,":[57],"back-end":[58],"dielectrics":[59],"MIMCAPs":[61],"thoroughly":[63],"characterized":[64],"proven":[66],"robust":[67],"throughout":[68],"a":[69,75],"10-year":[70],"lifetime.":[71],"results":[73],"reliable":[76],"that":[79],"compliant":[81],"industrial":[83],"standards":[84],"enable":[86],"high-voltage":[87],"requirements.":[89]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
