{"id":"https://openalex.org/W2945628190","doi":"https://doi.org/10.1109/irps.2019.8720563","title":"Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-\u03bcm CMOS Process","display_name":"Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-\u03bcm CMOS Process","publication_year":2019,"publication_date":"2019-03-01","ids":{"openalex":"https://openalex.org/W2945628190","doi":"https://doi.org/10.1109/irps.2019.8720563","mag":"2945628190"},"language":"en","primary_location":{"id":"doi:10.1109/irps.2019.8720563","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps.2019.8720563","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064308160","display_name":"Chuncheng Chen","orcid":"https://orcid.org/0000-0003-4034-8063"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chun-Cheng Chen","raw_affiliation_strings":["Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043540734","display_name":"Ming\u2010Dou Ker","orcid":"https://orcid.org/0000-0003-3622-181X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Dou Ker","raw_affiliation_strings":["Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5064308160"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.6032,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.68419836,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.9890072345733643},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6355615854263306},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.49989986419677734},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.44561246037483215},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.44442373514175415},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.43787774443626404},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4108036160469055},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3818429112434387},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32800665497779846},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.324466347694397},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.31576091051101685},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23797938227653503}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9890072345733643},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6355615854263306},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49989986419677734},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.44561246037483215},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.44442373514175415},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.43787774443626404},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4108036160469055},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3818429112434387},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32800665497779846},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.324466347694397},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.31576091051101685},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23797938227653503}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps.2019.8720563","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps.2019.8720563","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1494199278","https://openalex.org/W2005793633","https://openalex.org/W2006928005","https://openalex.org/W2088724906","https://openalex.org/W2119315371","https://openalex.org/W2141444414","https://openalex.org/W2143655922","https://openalex.org/W4251109733","https://openalex.org/W4299933435","https://openalex.org/W6677844482","https://openalex.org/W6681055347"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2730314563","https://openalex.org/W2058541779","https://openalex.org/W2006330903"],"abstract_inverted_index":{"This":[0],"work":[1],"studied":[2],"the":[3,41,45,62,74,96,109],"latch-up":[4,46,88,114],"path":[5,28,47],"between":[6,29,48],"two":[7,30],"PMOS":[8,31,50,53,97],"devices":[9,32,98],"powered":[10],"by":[11],"different":[12,100],"supply":[13],"voltages":[14],"in":[15,56,99],"a":[16,25],"0.18\u03bcm":[17],"CMOS":[18],"process.":[19],"In":[20,90],"IC":[21,94],"field":[22],"applications,":[23],"such":[24,86,112],"non-typical":[26],"latchup":[27],"was":[33,54],"ever":[34],"fired":[35],"to":[36,72,84,107],"cause":[37],"unrecoverable":[38],"failures.":[39],"Through":[40],"silicon":[42,63],"test":[43,67],"chip,":[44],"I/O":[49],"and":[51,80],"core":[52],"investigated":[55],"details.":[57],"The":[58],"measurement":[59],"results":[60],"from":[61],"chip":[64,91],"with":[65],"split":[66],"structures":[68],"can":[69],"be":[70,104],"used":[71],"investigate":[73],"design":[75],"rules":[76],"on":[77],"anode-to-cathode":[78],"spacing":[79],"guard":[81],"ring":[82],"placement":[83],"prevent":[85,108],"PMOS-to-PMOS":[87],"issue.":[89],"layout":[92],"of":[93,111],"products,":[95],"power":[101],"domains":[102],"shall":[103],"carefully":[105],"checked":[106],"occurrence":[110],"unexpected":[113],"path.":[115]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}
