{"id":"https://openalex.org/W2945947931","doi":"https://doi.org/10.1109/irps.2019.8720515","title":"A Comprehensive Wafer Level Reliability Study on 65nm Silicon Interposer","display_name":"A Comprehensive Wafer Level Reliability Study on 65nm Silicon Interposer","publication_year":2019,"publication_date":"2019-03-01","ids":{"openalex":"https://openalex.org/W2945947931","doi":"https://doi.org/10.1109/irps.2019.8720515","mag":"2945947931"},"language":"en","primary_location":{"id":"doi:10.1109/irps.2019.8720515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps.2019.8720515","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110257134","display_name":"CS Premachandran","orcid":null},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"CS Premachandran","raw_affiliation_strings":["GLOBALFOUNDRIESUS Inc., Malta, New York, USA"],"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIESUS Inc., Malta, New York, USA","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031382977","display_name":"Thuy Tran-Quinn","orcid":null},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thuy Tran-Quinn","raw_affiliation_strings":["GLOBALFOUNDRIESUS Inc., NY"],"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIESUS Inc., NY","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065068788","display_name":"Lloyd Burrell","orcid":null},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lloyd Burrell","raw_affiliation_strings":["GLOBALFOUNDRIESUS Inc., NY"],"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIESUS Inc., NY","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109955319","display_name":"Patrick Justison","orcid":null},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Justison","raw_affiliation_strings":["GLOBALFOUNDRIESUS Inc., Malta, New York, USA"],"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIESUS Inc., Malta, New York, USA","institution_ids":["https://openalex.org/I35662394"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110257134"],"corresponding_institution_ids":["https://openalex.org/I35662394"],"apc_list":null,"apc_paid":null,"fwci":0.4842,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.64961137,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12224","display_name":"Nanofabrication and Lithography Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interposer","display_name":"Interposer","score":0.9420956373214722},{"id":"https://openalex.org/keywords/electromigration","display_name":"Electromigration","score":0.7446236610412598},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.7186028957366943},{"id":"https://openalex.org/keywords/back-end-of-line","display_name":"Back end of line","score":0.6747913360595703},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.6719399690628052},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.6691733598709106},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6691461205482483},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.651238739490509},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5514904856681824},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.5248953104019165},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4733588397502899},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.46276846528053284},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.4567207098007202},{"id":"https://openalex.org/keywords/copper-interconnect","display_name":"Copper interconnect","score":0.41950464248657227},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.353055864572525},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.29699406027793884},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28645023703575134},{"id":"https://openalex.org/keywords/etching","display_name":"Etching (microfabrication)","score":0.20294734835624695},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1836441159248352},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.12700378894805908},{"id":"https://openalex.org/keywords/composite-material","display_name":"Composite material","score":0.07293376326560974},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06035444140434265}],"concepts":[{"id":"https://openalex.org/C158802814","wikidata":"https://www.wikidata.org/wiki/Q6056418","display_name":"Interposer","level":4,"score":0.9420956373214722},{"id":"https://openalex.org/C138055206","wikidata":"https://www.wikidata.org/wiki/Q1319010","display_name":"Electromigration","level":2,"score":0.7446236610412598},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.7186028957366943},{"id":"https://openalex.org/C2776628375","wikidata":"https://www.wikidata.org/wiki/Q4839229","display_name":"Back end of line","level":3,"score":0.6747913360595703},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.6719399690628052},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.6691733598709106},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6691461205482483},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.651238739490509},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5514904856681824},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.5248953104019165},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4733588397502899},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.46276846528053284},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.4567207098007202},{"id":"https://openalex.org/C116372231","wikidata":"https://www.wikidata.org/wiki/Q605757","display_name":"Copper interconnect","level":3,"score":0.41950464248657227},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.353055864572525},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29699406027793884},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28645023703575134},{"id":"https://openalex.org/C100460472","wikidata":"https://www.wikidata.org/wiki/Q2368605","display_name":"Etching (microfabrication)","level":3,"score":0.20294734835624695},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1836441159248352},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.12700378894805908},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.07293376326560974},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06035444140434265},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C133386390","wikidata":"https://www.wikidata.org/wiki/Q184996","display_name":"Dielectric","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps.2019.8720515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps.2019.8720515","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Reliability Physics Symposium (IRPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5899999737739563,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2512833993","https://openalex.org/W2620901297","https://openalex.org/W2749199255","https://openalex.org/W2886301043","https://openalex.org/W4289453669"],"related_works":["https://openalex.org/W1990828594","https://openalex.org/W2011182927","https://openalex.org/W2310189477","https://openalex.org/W2333804548","https://openalex.org/W2044721343","https://openalex.org/W2543304869","https://openalex.org/W2019002696","https://openalex.org/W2072269247","https://openalex.org/W2047315796","https://openalex.org/W2142764951"],"abstract_inverted_index":{"Stacking":[0],"of":[1,92,118],"chips":[2],"vertically":[3],"will":[4],"reduce":[5],"the":[6,29,70,119],"interconnection":[7],"resistance":[8],"and":[9,31,104,125],"as":[10,56],"a":[11,52,66,87,105],"result":[12],"enhance":[13],"data":[14],"communication":[15],"between":[16],"chips.":[17],"Memory":[18,41],"chip":[19,22,38],"to":[20,27,35,42],"logic":[21,43],"integration":[23,44],"requires":[24],"close":[25],"proximity":[26],"improve":[28],"performance":[30],"is":[32,69,84,121],"an":[33],"alternate":[34],"SOC":[36],"type":[37],"level":[39,116],"integration.":[40,58,76],"can":[45],"be":[46],"done":[47],"side":[48,50],"by":[49],"using":[51],"silicon":[53,67,82],"interposer,":[54],"known":[55],"2.5D":[57],"Copper":[59],"filled":[60],"through":[61],"Silicon":[62],"via":[63],"(TSV)":[64],"in":[65,112],"wafer":[68],"key":[71],"enabling":[72],"technology":[73],"for":[74],"this":[75,78,113],"In":[77],"paper":[79],"100um":[80],"thin":[81],"interposer":[83,103,107,120],"fabricated":[85],"with":[86,98,123],"3":[88],"BEOL":[89],"(Back":[90],"end":[91],"line)":[93],"metal":[94],"process":[95],"having":[96],"TSV":[97],"10um":[99],"diameter.":[100],"A":[101],"standard":[102],"stitched":[106],"reliability":[108,117],"challenges":[109],"are":[110],"described":[111],"paper.":[114],"Wafer":[115],"studied":[122],"electromigration":[124],"stress-migration.":[126]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2026-04-20T07:46:08.049788","created_date":"2025-10-10T00:00:00"}