{"id":"https://openalex.org/W2064376323","doi":"https://doi.org/10.1109/ipdpsw.2013.127","title":"A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications","display_name":"A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications","publication_year":2013,"publication_date":"2013-05-01","ids":{"openalex":"https://openalex.org/W2064376323","doi":"https://doi.org/10.1109/ipdpsw.2013.127","mag":"2064376323"},"language":"en","primary_location":{"id":"doi:10.1109/ipdpsw.2013.127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdpsw.2013.127","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.openaccessrepository.it/record/22516","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086932958","display_name":"Gianluca Durelli","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Gianluca Durelli","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105935100","display_name":"Alessandro Antonio Nacci","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro A. Nacci","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021243055","display_name":"Riccardo Cattaneo","orcid":"https://orcid.org/0000-0002-1520-4271"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Riccardo Cattaneo","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072400487","display_name":"Christian Pilato","orcid":"https://orcid.org/0000-0001-9315-1788"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Christian Pilato","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010543929","display_name":"Marco D. Santambrogio","orcid":"https://orcid.org/0000-0002-9883-9693"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco D. Santambrogio","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5086932958"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15150077,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"192","last_page":"201"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.9354972839355469},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8774570226669312},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8013412356376648},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7239190340042114},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6051342487335205},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5486689805984497},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.5301376581192017},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4769269824028015},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36360761523246765},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35829561948776245},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07890132069587708}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9354972839355469},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8774570226669312},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8013412356376648},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7239190340042114},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6051342487335205},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5486689805984497},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.5301376581192017},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4769269824028015},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36360761523246765},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35829561948776245},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07890132069587708},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/ipdpsw.2013.127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdpsw.2013.127","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/736967","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/736967","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:zenodo.org:22516","is_oa":true,"landing_page_url":"https://www.openaccessrepository.it/record/22516","pdf_url":null,"source":{"id":"https://openalex.org/S4306402478","display_name":"INFM-OAR (INFN Catania)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210116497","host_organization_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Catania","host_organization_lineage":["https://openalex.org/I4210116497"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"},{"id":"pmh:oai:zenodo.org:3444511","is_oa":true,"landing_page_url":"https://zenodo.org/record/3444511","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"}],"best_oa_location":{"id":"pmh:oai:zenodo.org:22516","is_oa":true,"landing_page_url":"https://www.openaccessrepository.it/record/22516","pdf_url":null,"source":{"id":"https://openalex.org/S4306402478","display_name":"INFM-OAR (INFN Catania)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210116497","host_organization_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Catania","host_organization_lineage":["https://openalex.org/I4210116497"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G5853450275","display_name":"Facilitating Analysis and Synthesis Technologies\\nfor Effective Reconfiguration","funder_award_id":"287804","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1498175716","https://openalex.org/W1569403313","https://openalex.org/W1967640490","https://openalex.org/W1982565841","https://openalex.org/W1990029071","https://openalex.org/W2008934398","https://openalex.org/W2057716210","https://openalex.org/W2101633590","https://openalex.org/W2104674486","https://openalex.org/W2115493560","https://openalex.org/W2123184444","https://openalex.org/W2125662502","https://openalex.org/W2125971799","https://openalex.org/W2127044011","https://openalex.org/W2143342758","https://openalex.org/W2143712034","https://openalex.org/W2153625096","https://openalex.org/W2153911262","https://openalex.org/W2160642395","https://openalex.org/W2537136437","https://openalex.org/W4247321183","https://openalex.org/W6647797989","https://openalex.org/W6681109464","https://openalex.org/W6728877621"],"related_works":["https://openalex.org/W2293118914","https://openalex.org/W2998381397","https://openalex.org/W4236419692","https://openalex.org/W3167919718","https://openalex.org/W4251718783","https://openalex.org/W2999668243","https://openalex.org/W1998888015","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Dataflow":[0],"applications":[1],"have":[2],"proven":[3],"to":[4,11,26,45,72,96,110],"be":[5,30,46],"well-suited":[6],"for":[7],"hardware":[8,49],"implementation":[9],"due":[10],"their":[12],"intrinsic":[13],"pipelined":[14],"nature.":[15],"Furthermore":[16],"a":[17,66],"wide":[18],"range":[19],"of":[20,77,86],"algorithms,":[21],"ranging":[22],"from":[23],"image":[24],"analysis":[25,85],"map-reduce":[27],"tasks,":[28],"can":[29],"expressed":[31],"using":[32],"this":[33,62],"paradigm.":[34],"At":[35],"the":[36,75,87,98,105,114],"same":[37,115],"time":[38,116],"Field":[39],"Programmable":[40],"Gate":[41],"Arrays":[42],"(FPGA)":[43],"start":[44],"employed":[47],"as":[48],"accelerators":[50],"also":[51],"in":[52,103],"high-end":[53],"systems":[54],"coupled":[55],"with":[56],"General":[57],"Purpose":[58],"Processors":[59],"(GPP).":[60],"In":[61],"work":[63],"we":[64],"propose":[65],"programmable":[67],"interconnection":[68],"structure":[69],"which":[70],"permits":[71],"dynamically":[73],"reconfigure":[74],"functionality":[76],"an":[78],"FPGA":[79],"implementing":[80],"dataflow":[81],"applications.":[82],"A":[83],"detailed":[84],"proposed":[88],"solution":[89],"shows":[90],"that":[91],"it":[92],"is":[93],"effectively":[94],"able":[95],"increase":[97],"overall":[99,106],"system":[100],"flexibility":[101],"helping":[102],"reducing":[104,117],"workload":[107],"execution":[108],"up":[109],"25%,":[111],"while":[112],"at":[113],"its":[118],"variance.":[119]},"counts_by_year":[],"updated_date":"2026-03-11T14:59:36.786465","created_date":"2016-06-24T00:00:00"}