{"id":"https://openalex.org/W1987821767","doi":"https://doi.org/10.1109/ipdpsw.2010.5470821","title":"Programming customized parallel architectures in FPGA","display_name":"Programming customized parallel architectures in FPGA","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W1987821767","doi":"https://doi.org/10.1109/ipdpsw.2010.5470821","mag":"1987821767"},"language":"en","primary_location":{"id":"doi:10.1109/ipdpsw.2010.5470821","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdpsw.2010.5470821","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Symposium on Parallel &amp; Distributed Processing, Workshops and Phd Forum (IPDPSW)","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010411820","display_name":"I. Bolsens","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ivo Bolsens","raw_affiliation_strings":["Xilinx Corporation, San Jose, CA, USA","Xilinx, San Jose, California, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx, San Jose, California, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5010411820"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9847999811172485,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9847999811172485,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9840999841690063,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9767000079154968,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8616873025894165},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5970070958137512},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5669550895690918},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.5519775152206421},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5330259799957275},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4834917187690735},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.44604694843292236},{"id":"https://openalex.org/keywords/memory-model","display_name":"Memory model","score":0.4259773790836334},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.4202222228050232},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4194498658180237},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41940340399742126},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4069664776325226},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.34835848212242126},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2095804214477539},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.142995685338974}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8616873025894165},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5970070958137512},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5669550895690918},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.5519775152206421},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5330259799957275},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4834917187690735},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.44604694843292236},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.4259773790836334},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4202222228050232},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4194498658180237},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41940340399742126},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4069664776325226},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.34835848212242126},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2095804214477539},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.142995685338974},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdpsw.2010.5470821","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdpsw.2010.5470821","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Symposium on Parallel &amp; Distributed Processing, Workshops and Phd Forum (IPDPSW)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W4317827391","https://openalex.org/W2182797201","https://openalex.org/W2124489231","https://openalex.org/W4233212676","https://openalex.org/W2186451538","https://openalex.org/W1839004754","https://openalex.org/W40577698","https://openalex.org/W2078898826","https://openalex.org/W1496676675"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"CPUs":[4],"are":[5,68,83,102],"multicore":[6],"(and":[7],"multi-cache)":[8],"supported":[9],"by":[10],"a":[11,19,39,50],"coherent,":[12],"global,":[13],"shared":[14,86],"memory":[15,29,33,87,121],"model.":[16],"FPGAs":[17],"offer":[18],"vast":[20],"number":[21],"of":[22,47,72,93,115],"distributed":[23,28,32,65],"programmable":[24],"function":[25],"blocks":[26,30],"and":[27,64,79,112],"across":[31],"spaces.":[34],"This":[35],"presentation":[36],"will":[37],"discuss":[38],"hybrid":[40,74,95],"computing":[41,96],"architecture":[42],"that":[43],"unifies":[44],"the":[45,70,73,77,90,94,109,116],"development":[46],"applications":[48],"for":[49],"combined":[51],"CPU-FPGA":[52],"platform.":[53,97],"The":[54],"proposed":[55],"programming":[56,128],"model":[57],"is":[58],"based":[59],"on":[60,89],"message":[61],"passing":[62],"(MPI)":[63],"memory.":[66],"NoCs":[67,82,101,118],"at":[69],"heart":[71],"platform":[75],"managing":[76],"control":[78],"data":[80],"flows.":[81],"implemented":[84,103],"through":[85],"buffers":[88],"CPU":[91],"portion":[92],"On":[98],"parallel":[99],"hardware,":[100],"as":[104,131],"application-specific":[105,120],"point-to-point":[106],"networks":[107],"exploiting":[108],"abundant":[110],"routing":[111],"switching":[113],"resources":[114],"FPGA.":[117],"enable":[119],"models":[122,129],"while":[123],"keeping":[124],"with":[125],"standard,":[126],"familiar":[127],"such":[130],"MPI.":[132]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
