{"id":"https://openalex.org/W1978408137","doi":"https://doi.org/10.1109/ipdpsw.2010.5470747","title":"High-level synthesis techniques for in-circuit assertion-based verification","display_name":"High-level synthesis techniques for in-circuit assertion-based verification","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W1978408137","doi":"https://doi.org/10.1109/ipdpsw.2010.5470747","mag":"1978408137"},"language":"en","primary_location":{"id":"doi:10.1109/ipdpsw.2010.5470747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdpsw.2010.5470747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Symposium on Parallel &amp; Distributed Processing, Workshops and Phd Forum (IPDPSW)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037652483","display_name":"John Curreri","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"John Curreri","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA"],"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088031457","display_name":"Greg Stitt","orcid":"https://orcid.org/0000-0001-7159-7439"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Stitt","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA"],"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082898376","display_name":"Alan D. George","orcid":"https://orcid.org/0000-0001-9665-2879"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan D. George","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA"],"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037652483"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":0.7491,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.71359738,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8047691583633423},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7917712330818176},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.758321225643158},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.673272430896759},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6397982835769653},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.507283627986908},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.49702003598213196},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.49510684609413147},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4696345329284668},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4287128448486328},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3230815529823303},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12482807040214539}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8047691583633423},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7917712330818176},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.758321225643158},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.673272430896759},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6397982835769653},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.507283627986908},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.49702003598213196},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.49510684609413147},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4696345329284668},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4287128448486328},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3230815529823303},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12482807040214539}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdpsw.2010.5470747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdpsw.2010.5470747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Symposium on Parallel &amp; Distributed Processing, Workshops and Phd Forum (IPDPSW)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1527905812","https://openalex.org/W1543657314","https://openalex.org/W1784406605","https://openalex.org/W1998778168","https://openalex.org/W2096454445","https://openalex.org/W2098178883","https://openalex.org/W2121851099","https://openalex.org/W2129183345","https://openalex.org/W2145125458","https://openalex.org/W2146399815","https://openalex.org/W2147910407"],"related_works":["https://openalex.org/W2794617843","https://openalex.org/W2365569181","https://openalex.org/W3202354107","https://openalex.org/W4306967480","https://openalex.org/W2168113051","https://openalex.org/W2348758434","https://openalex.org/W2165456233","https://openalex.org/W2005854230","https://openalex.org/W2090808187","https://openalex.org/W2122042448"],"abstract_inverted_index":{"Field-Programmable":[0],"Gate":[1],"Arrays":[2],"(FPGAs)":[3],"are":[4],"increasingly":[5],"employed":[6],"in":[7,95],"both":[8],"high-performance":[9],"computing":[10],"and":[11,17,54,85,118,129,161],"embedded":[12],"systems":[13,105],"due":[14],"to":[15,21,59,74,115,171],"performance":[16,164],"power":[18],"advantages":[19],"compared":[20,170],"microprocessors.":[22],"However,":[23],"widespread":[24],"usage":[25],"of":[26,87],"FPGAs":[27],"has":[28,37],"been":[29],"limited":[30],"by":[31,125,134,156,165],"increased":[32],"design":[33],"complexity.":[34],"Highlevel":[35],"synthesis":[36,68],"reduced":[38,153],"this":[39,63],"complexity":[40],"but":[41],"often":[42],"relies":[43],"on":[44,143],"inaccurate":[45],"software":[46,60,113],"simulation":[47],"or":[48],"lengthy":[49],"register-transfer-level":[50],"simulations":[51],"for":[52,103,138],"verification":[53,84],"debugging,":[55],"which":[56],"is":[57],"unattractive":[58],"developers.":[61],"In":[62],"paper,":[64],"we":[65],"present":[66],"high-level":[67],"techniques":[69,111,152],"that":[70],"allow":[71],"application":[72,140],"designers":[73],"efficiently":[75],"synthesize":[76],"ANSI-C":[77],"assertions":[78],"into":[79],"FPGA":[80,98,120,131],"circuits,":[81],"enabling":[82],"real-time":[83],"debugging":[86],"circuits":[88],"generated":[89],"from":[90],"highlevel":[91],"languages,":[92],"while":[93,122],"executing":[94],"the":[96,109],"actual":[97],"environment.":[99],"Although":[100],"not":[101],"appropriate":[102],"all":[104],"(e.g.,":[106],"safety-critical":[107],"systems),":[108],"proposed":[110],"enable":[112],"developers":[114],"rapidly":[116],"verify":[117],"debug":[119],"applications,":[121],"reducing":[123],"frequency":[124],"less":[126,135],"than":[127,136],"3%":[128],"increasing":[130],"resource":[132],"utilization":[133],"0.13%":[137],"several":[139],"case":[141],"studies":[142],"an":[144],"Altera":[145],"Stratix-II":[146],"EP2S180":[147],"using":[148],"Impulse-C.":[149],"The":[150],"presented":[151],"area":[154],"overhead":[155],"as":[157,159,166,168],"much":[158,167],"3x":[160],"improved":[162],"assertion":[163],"100%":[169],"unoptimized":[172],"in-circuit":[173],"assertions.":[174]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
