{"id":"https://openalex.org/W3140501673","doi":"https://doi.org/10.1109/ipdps.2006.1639549","title":"Efficient hardware algorithms for n choose k counters","display_name":"Efficient hardware algorithms for n choose k counters","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3140501673","doi":"https://doi.org/10.1109/ipdps.2006.1639549","mag":"3140501673"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2006.1639549","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639549","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009547258","display_name":"Yasuaki Ito","orcid":"https://orcid.org/0000-0003-0593-231X"},"institutions":[{"id":"https://openalex.org/I113306721","display_name":"Hiroshima University","ror":"https://ror.org/03t78wx29","country_code":"JP","type":"education","lineage":["https://openalex.org/I113306721"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Y. Ito","raw_affiliation_strings":["Graduate School of Engineering, Hiroshima University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Hiroshima University, Japan","institution_ids":["https://openalex.org/I113306721"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086055038","display_name":"Koji Nakano","orcid":"https://orcid.org/0000-0002-2040-4032"},"institutions":[{"id":"https://openalex.org/I113306721","display_name":"Hiroshima University","ror":"https://ror.org/03t78wx29","country_code":"JP","type":"education","lineage":["https://openalex.org/I113306721"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Nakano","raw_affiliation_strings":["Graduate School of Engineering, Hiroshima University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Hiroshima University, Japan","institution_ids":["https://openalex.org/I113306721"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047381005","display_name":"Y. Yamagishi","orcid":null},"institutions":[{"id":"https://openalex.org/I113306721","display_name":"Hiroshima University","ror":"https://ror.org/03t78wx29","country_code":"JP","type":"education","lineage":["https://openalex.org/I113306721"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Yamagishi","raw_affiliation_strings":["Graduate School of Engineering, Hiroshima University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Hiroshima University, Japan","institution_ids":["https://openalex.org/I113306721"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009547258"],"corresponding_institution_ids":["https://openalex.org/I113306721"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.42904809,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"e86 d","issue":null,"first_page":"8 pp.","last_page":"8 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12923","display_name":"Digital Image Processing Techniques","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12923","display_name":"Digital Image Processing Techniques","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9833999872207642,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9785000085830688,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.7128410339355469},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6748533248901367},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6369617581367493},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5269915461540222},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.43078869581222534},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38251689076423645},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3559994101524353},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3256862163543701},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1661267876625061},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0734938383102417},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06783604621887207},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.06244075298309326}],"concepts":[{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.7128410339355469},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6748533248901367},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6369617581367493},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5269915461540222},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.43078869581222534},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38251689076423645},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3559994101524353},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3256862163543701},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1661267876625061},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0734938383102417},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06783604621887207},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.06244075298309326}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2006.1639549","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639549","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1500798974","https://openalex.org/W1594474980","https://openalex.org/W2005874499","https://openalex.org/W2011914019","https://openalex.org/W2752885492","https://openalex.org/W4248226820","https://openalex.org/W4299935650","https://openalex.org/W6635737572","https://openalex.org/W6830266831"],"related_works":["https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W2144453115","https://openalex.org/W2128223750","https://openalex.org/W4238532390","https://openalex.org/W2188872161","https://openalex.org/W2961779879","https://openalex.org/W797688974","https://openalex.org/W2002978035","https://openalex.org/W2209382646"],"abstract_inverted_index":{"An":[0],"\"n":[1,27],"choose":[2,28],"k\"":[3,29],"counter":[4,7,12,30],"(C(n,":[5],"k)":[6,21,57,63,83],"for":[8,68,86,112],"short)":[9],"is":[10,47,74,127],"a":[11],"which":[13],"lists":[14],"all":[15],"n-bit":[16],"numbers":[17],"with":[18],"(n":[19],"-":[20],"0's":[22],"and":[23,38,97,108],"k":[24],"1's.":[25],"The":[26,41,71],"has":[31],"applications":[32],"to":[33,48,75],"solving":[34],"combinatorial":[35],"optimization":[36],"problems":[37],"image":[39],"processing.":[40],"main":[42],"contribution":[43,73],"of":[44,54,93,102,105,140],"this":[45],"work":[46],"present":[49],"an":[50],"efficient":[51,78],"hardware":[52],"implementation":[53,96,126],"the":[55,91,103,109,113,120,129,143],"C(n,":[56,62,82],"counter.":[58],"In":[59],"some":[60],"applications,":[61],"counters":[64,84],"are":[65],"used":[66,106],"only":[67,85],"small":[69,87],"k.":[70,88],"second":[72],"show":[76],"more":[77],"implementations":[79,99,145],"that":[80,124],"support":[81],"We":[89],"evaluate":[90],"performance":[92],"our":[94,125],"new":[95],"known":[98],"in":[100,133],"terms":[101],"number":[104,139],"slices":[107,141],"clock":[110,135],"frequency":[111,136],"Xilinx":[114],"VirtexII":[115],"family":[116],"FPGA":[117],"XC2V3000-4.":[118],"Although":[119],"theoretical":[121],"analysis":[122],"shows":[123],"not":[128],"best,":[130],"it":[131],"runs":[132],"higher":[134],"using":[137],"fewer":[138],"than":[142],"other":[144]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}