{"id":"https://openalex.org/W3146798838","doi":"https://doi.org/10.1109/ipdps.2006.1639490","title":"Power consumption advantage of a dynamic optically reconfigurable gate array","display_name":"Power consumption advantage of a dynamic optically reconfigurable gate array","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3146798838","doi":"https://doi.org/10.1109/ipdps.2006.1639490","mag":"3146798838"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2006.1639490","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639490","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101887712","display_name":"Minoru Watanabe","orcid":"https://orcid.org/0000-0002-7452-3555"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Watanabe","raw_affiliation_strings":["Department of Systems Innovation and Informatics, Kyushu Institute of Technology, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Systems Innovation and Informatics, Kyushu Institute of Technology, Fukuoka, Japan","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023929616","display_name":"Fumihisa Kobayashi","orcid":"https://orcid.org/0000-0002-1903-0125"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"F. Kobayashi","raw_affiliation_strings":["Department of Systems Innovation and Informatics, Kyushu Institute of Technology, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Systems Innovation and Informatics, Kyushu Institute of Technology, Fukuoka, Japan","institution_ids":["https://openalex.org/I207014233"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101887712"],"corresponding_institution_ids":["https://openalex.org/I207014233"],"apc_list":null,"apc_paid":null,"fwci":0.2787,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61815486,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"56","issue":null,"first_page":"4 pp.","last_page":"4 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8826428055763245},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8409978151321411},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.6894716024398804},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.594632625579834},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5658062696456909},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5311046242713928},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5237433910369873},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.48898041248321533},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.47399818897247314},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4645020663738251},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43983593583106995},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3840310573577881},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3647669553756714},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.351493239402771},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26517242193222046},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.20482638478279114},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08375352621078491},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.07288870215415955}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8826428055763245},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8409978151321411},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.6894716024398804},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.594632625579834},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5658062696456909},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5311046242713928},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5237433910369873},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.48898041248321533},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.47399818897247314},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4645020663738251},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43983593583106995},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3840310573577881},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3647669553756714},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.351493239402771},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26517242193222046},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.20482638478279114},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08375352621078491},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.07288870215415955},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2006.1639490","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639490","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320912","display_name":"Ministry of Education, Culture, Sports, Science and Technology","ror":"https://ror.org/048rj2z13"},{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334789","display_name":"Japan Science and Technology Agency","ror":"https://ror.org/00097mb19"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W193742818","https://openalex.org/W1500064396","https://openalex.org/W1866628693","https://openalex.org/W1941487794","https://openalex.org/W2032100948","https://openalex.org/W2083398496","https://openalex.org/W2128239317","https://openalex.org/W2135931973","https://openalex.org/W2155814884","https://openalex.org/W6607954651","https://openalex.org/W7061034308"],"related_works":["https://openalex.org/W2165091308","https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2034458695","https://openalex.org/W2340647897","https://openalex.org/W2500205862","https://openalex.org/W2014165129","https://openalex.org/W150753669","https://openalex.org/W2038293309"],"abstract_inverted_index":{"Optically":[0],"reconfigurable":[1],"gate":[2,11,41,55,90],"arrays":[3],"(ORGAs)":[4],"are":[5,138],"a":[6,60,73,88,125],"type":[7],"of":[8,34,49,57,87,96,118,124,134],"field":[9],"programmable":[10],"array":[12],"(FPGA).":[13],"However,":[14,39],"unlike":[15],"FPGAs,":[16],"an":[17],"ORGA":[18,62],"can":[19,66],"quickly":[20],"be":[21],"reconfigured":[22],"optically":[23],"using":[24],"external":[25],"optical":[26,29,120],"memories":[27],"and":[28],"connections.":[30],"Recently,":[31],"various":[32],"types":[33],"ORGAs":[35,144],"have":[36],"been":[37,77,108],"developed.":[38],"their":[40],"counts":[42],"were":[43],"not":[44,83],"satisfactory":[45],"compared":[46],"with":[47,142],"those":[48],"FPGAs.":[50],"Therefore,":[51],"to":[52,71],"improve":[53],"the":[54,85,94,119,130,135],"density":[56],"conventional":[58],"ORGAs,":[59],"dynamic":[61],"(DORGA)":[63],"architecture":[64,81,137],"that":[65,111],"remove":[67],"static":[68],"memory":[69],"functions":[70],"store":[72],"configuration":[74],"context":[75],"has":[76,106],"proposed.":[78],"The":[79],"DORGA":[80,136],"offers":[82],"only":[84],"advantages":[86,133],"high":[89],"count,":[91],"but":[92],"also":[93],"advantage":[95],"low":[97],"reconfiguration":[98,121],"power":[99,104,122,131],"consumption.":[100],"To":[101],"date,":[102],"its":[103],"consumption":[105,123,132],"never":[107],"clarified.":[109],"For":[110],"reason,":[112],"this":[113],"paper":[114],"presents":[115],"measurement":[116],"results":[117],"DORGA-VLSI":[126],"chip.":[127],"In":[128],"addition,":[129],"clarified":[139],"through":[140],"comparison":[141],"other":[143]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
