{"id":"https://openalex.org/W3140242952","doi":"https://doi.org/10.1109/ipdps.2006.1639484","title":"Design space exploration for low-power reconfigurable fabrics","display_name":"Design space exploration for low-power reconfigurable fabrics","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3140242952","doi":"https://doi.org/10.1109/ipdps.2006.1639484","mag":"3140242952"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2006.1639484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078470359","display_name":"Gayatri Mehta","orcid":"https://orcid.org/0000-0001-7754-1874"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"G. Mehta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113801969","display_name":"R. Hoare","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R.R. Hoare","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036209558","display_name":"Justin Stander","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Stander","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030875484","display_name":"Alex K. Jones","orcid":"https://orcid.org/0000-0001-7498-0206"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A.K. Jones","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5078470359"],"corresponding_institution_ids":["https://openalex.org/I170201317"],"apc_list":null,"apc_paid":null,"fwci":0.5573,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.69830363,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"4 pp.","last_page":"4 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7646888494491577},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6895565986633301},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6218506693840027},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6177146434783936},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5828613638877869},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5682040452957153},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.462864488363266},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.443510502576828},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.43941348791122437},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4355788826942444},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.429837167263031},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4254467189311981},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4172346293926239},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.41420263051986694},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4028494954109192},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39614298939704895},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3260260224342346},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2122030258178711},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13154593110084534}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7646888494491577},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6895565986633301},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6218506693840027},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6177146434783936},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5828613638877869},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5682040452957153},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.462864488363266},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.443510502576828},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.43941348791122437},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4355788826942444},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.429837167263031},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4254467189311981},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4172346293926239},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.41420263051986694},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4028494954109192},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39614298939704895},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3260260224342346},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2122030258178711},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13154593110084534},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2006.1639484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1714829617","https://openalex.org/W1748435361","https://openalex.org/W1887556625","https://openalex.org/W2078262581","https://openalex.org/W2088071292","https://openalex.org/W2112651436","https://openalex.org/W2139900512","https://openalex.org/W2163196846","https://openalex.org/W2164939754","https://openalex.org/W6639711652","https://openalex.org/W6670054089","https://openalex.org/W6672882328","https://openalex.org/W6680296641"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W2135118255","https://openalex.org/W215057456","https://openalex.org/W1500063550","https://openalex.org/W2106366463","https://openalex.org/W2165891825","https://openalex.org/W2942050196","https://openalex.org/W4251805775","https://openalex.org/W3005710104","https://openalex.org/W3092334294"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"parameterizable,":[4],"coarse":[5],"grained,":[6],"reconfigurable":[7],"fabric":[8],"model":[9],"that":[10],"attempts":[11],"to":[12,51,63,101],"maintain":[13],"field":[14],"programmable":[15],"gate":[16],"array":[17],"(FPGA)-like":[18],"programmability":[19],"and":[20,60,73],"computer":[21],"aided":[22],"design":[23,44],"(CAD),":[24],"with":[25],"application":[26],"specific":[27],"integrated":[28],"circuit":[29],"(ASIC)-like":[30],"power":[31,105],"characteristics":[32],"for":[33],"digital":[34],"signal":[35,92],"processing":[36,93],"(DSP)":[37],"style":[38],"applications.":[39],"Using":[40],"this":[41],"model,":[42],"architectural":[43],"space":[45],"decisions":[46],"are":[47],"explored":[48],"in":[49],"order":[50],"define":[52],"an":[53],"energy-efficient":[54],"fabric.":[55,97],"The":[56,79,98],"impact":[57],"on":[58],"energy":[59],"performance":[61],"due":[62],"the":[64,91,96,102],"variation":[65],"of":[66,90,104],"different":[67],"parameters":[68],"such":[69],"as":[70],"data":[71],"width":[72,108],"interconnection":[74],"flexibility":[75],"has":[76,83],"been":[77,85],"studied.":[78],"multiplexer":[80],"cardinality":[81,114],"usage":[82],"also":[84],"studied":[86],"by":[87,112],"mapping":[88],"some":[89],"applications":[94],"onto":[95],"results":[99],"point":[100],"use":[103],"optimized":[106],"32-bit":[107],"computational":[109],"elements":[110],"interconnected":[111],"low":[113],"multiplexers":[115],"like":[116],"4:1":[117],"multiplexers.":[118]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}