{"id":"https://openalex.org/W4254375469","doi":"https://doi.org/10.1109/ipdps.2006.1639455","title":"Selection of instruction set extensions for an FPGA embedded processor core","display_name":"Selection of instruction set extensions for an FPGA embedded processor core","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W4254375469","doi":"https://doi.org/10.1109/ipdps.2006.1639455"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2006.1639455","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639455","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046094792","display_name":"B.F. Veale","orcid":null},"institutions":[{"id":"https://openalex.org/I8692664","display_name":"University of Oklahoma","ror":"https://ror.org/02aqsxs83","country_code":"US","type":"education","lineage":["https://openalex.org/I8692664"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"B.F. Veale","raw_affiliation_strings":["School of Computer Science, University of Oklahama, Norman, OK, USA"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Oklahama, Norman, OK, USA","institution_ids":["https://openalex.org/I8692664"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010786051","display_name":"J.K. Antonio","orcid":null},"institutions":[{"id":"https://openalex.org/I8692664","display_name":"University of Oklahoma","ror":"https://ror.org/02aqsxs83","country_code":"US","type":"education","lineage":["https://openalex.org/I8692664"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.K. Antonio","raw_affiliation_strings":["School of Computer Science, University of Oklahama, Norman, OK, USA"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Oklahama, Norman, OK, USA","institution_ids":["https://openalex.org/I8692664"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002624744","display_name":"M.P. Tull","orcid":null},"institutions":[{"id":"https://openalex.org/I8692664","display_name":"University of Oklahoma","ror":"https://ror.org/02aqsxs83","country_code":"US","type":"education","lineage":["https://openalex.org/I8692664"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.P. Tull","raw_affiliation_strings":["School of Electrical and Computer Engineering, University of Oklahama, Norman, OK, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, University of Oklahama, Norman, OK, USA","institution_ids":["https://openalex.org/I8692664"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006623568","display_name":"S.A. Jones","orcid":null},"institutions":[{"id":"https://openalex.org/I8692664","display_name":"University of Oklahoma","ror":"https://ror.org/02aqsxs83","country_code":"US","type":"education","lineage":["https://openalex.org/I8692664"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.A. Jones","raw_affiliation_strings":["School of Computer Science, University of Oklahama, Norman, OK, USA"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Oklahama, Norman, OK, USA","institution_ids":["https://openalex.org/I8692664"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5046094792"],"corresponding_institution_ids":["https://openalex.org/I8692664"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.41552802,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"8 pp.","last_page":"8 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/powerpc","display_name":"PowerPC","score":0.9922742247581482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7937633991241455},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.7081607580184937},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6928717494010925},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6639496684074402},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.5815112590789795},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.570525050163269},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5150465965270996},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4647597074508667},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45685508847236633},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.44060513377189636},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36270442605018616},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31065866351127625},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14533835649490356}],"concepts":[{"id":"https://openalex.org/C56005371","wikidata":"https://www.wikidata.org/wiki/Q209860","display_name":"PowerPC","level":3,"score":0.9922742247581482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7937633991241455},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.7081607580184937},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6928717494010925},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6639496684074402},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.5815112590789795},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.570525050163269},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5150465965270996},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4647597074508667},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45685508847236633},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.44060513377189636},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36270442605018616},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31065866351127625},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14533835649490356}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2006.1639455","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639455","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1581710334","https://openalex.org/W1686420892","https://openalex.org/W2036548030","https://openalex.org/W2075921636","https://openalex.org/W2077157218","https://openalex.org/W2080199699","https://openalex.org/W2159943047","https://openalex.org/W4230935926","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W4248794057","https://openalex.org/W1995817803","https://openalex.org/W2055341571","https://openalex.org/W3151101169","https://openalex.org/W2521544769","https://openalex.org/W3217472777","https://openalex.org/W98758690","https://openalex.org/W829028141","https://openalex.org/W4254375469","https://openalex.org/W2134552287"],"abstract_inverted_index":{"A":[0],"design":[1,77],"process":[2,78],"is":[3,21,37,58,134],"presented":[4],"for":[5,15,82],"the":[6,16,24,34,44,54,69,73,97,107,114,117,138,148],"selection":[7],"of":[8,11,28,33,52,72,116,124,150],"a":[9,59,83],"set":[10,13,32,49],"instruction":[12,31,48],"extensions":[14],"PowerPC":[17,35,47,55,109,118,139],"405":[18,36,56,119,140],"processor":[19,141],"that":[20,99],"embedded":[22,126],"into":[23],"Xilinx":[25],"Virtex":[26],"family":[27],"FPGAs.":[29],"The":[30,61,75],"extended":[38],"by":[39,154],"selecting":[40],"additional":[41],"instructions":[42,63,105],"from":[43,106],"full":[45,108],"32-bit":[46],"architecture":[50],"(ISA),":[51],"which":[53],"ISA":[57,110,115],"subset.":[60],"selected":[62,104],"are":[64,92,111],"supported":[65],"in":[66],"hardware":[67],"using":[68],"reconfigurable":[70],"resources":[71],"FPGA.":[74],"proposed":[76],"gathers":[79],"execution":[80],"statistics":[81,91],"target":[84],"application":[85],"through":[86,147],"profiling":[87],"or":[88],"simulation.":[89],"These":[90],"then":[93],"used":[94,135],"to":[95,113,136,142],"estimate":[96],"speedup":[98,130],"would":[100],"be":[101],"achieved":[102],"if":[103],"added":[112],"processor.":[120],"An":[121],"experimental":[122],"study":[123],"two":[125],"benchmarks":[127],"show":[128],"significant":[129],"when":[131],"this":[132],"approach":[133],"extend":[137],"support":[143],"various":[144],"floating-point":[145,151],"operations":[146],"use":[149],"cores":[152],"developed":[153],"QinetiQ.":[155]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
