{"id":"https://openalex.org/W3147849433","doi":"https://doi.org/10.1109/ipdps.2006.1639438","title":"A high-level target-precise model for designing reconfigurable HW tasks","display_name":"A high-level target-precise model for designing reconfigurable HW tasks","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3147849433","doi":"https://doi.org/10.1109/ipdps.2006.1639438","mag":"3147849433"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2006.1639438","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004122593","display_name":"Maik Boden","orcid":null},"institutions":[{"id":"https://openalex.org/I4210124274","display_name":"Fraunhofer Institute for Integrated Circuits","ror":"https://ror.org/024ape423","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210124274","https://openalex.org/I4923324"]},{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"M. Boden","raw_affiliation_strings":["Fraunhofer IIS, Dresden, Germany","Fraunhofer IIS EAS Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Fraunhofer IIS, Dresden, Germany","institution_ids":["https://openalex.org/I4210124274"]},{"raw_affiliation_string":"Fraunhofer IIS EAS Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043811259","display_name":"S. R\u00fclke","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]},{"id":"https://openalex.org/I4210124274","display_name":"Fraunhofer Institute for Integrated Circuits","ror":"https://ror.org/024ape423","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Rulke","raw_affiliation_strings":["Fraunhofer IIS, Dresden, Germany","Fraunhofer IIS EAS Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Fraunhofer IIS, Dresden, Germany","institution_ids":["https://openalex.org/I4210124274"]},{"raw_affiliation_string":"Fraunhofer IIS EAS Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024739574","display_name":"J\u00fcrgen Becker","orcid":"https://orcid.org/0000-0002-5082-5487"},"institutions":[{"id":"https://openalex.org/I4210119349","display_name":"Karlsruhe University of Education","ror":"https://ror.org/01t1kq612","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210119349"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J. Becker","raw_affiliation_strings":["University of Karlsruhe, Karlsruhe, Germany"],"affiliations":[{"raw_affiliation_string":"University of Karlsruhe, Karlsruhe, Germany","institution_ids":["https://openalex.org/I4210119349"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5004122593"],"corresponding_institution_ids":["https://openalex.org/I4210095661","https://openalex.org/I4210124274"],"apc_list":null,"apc_paid":null,"fwci":0.2787,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61857854,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"8 pp.","last_page":"8 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8159231543540955},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.750752329826355},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.6290391683578491},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6146162748336792},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.6143218874931335},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5687161684036255},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5553250312805176},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5547585487365723},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5192908644676208},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.4998054504394531},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4794665575027466},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4389117956161499},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.41334858536720276},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2972690761089325},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.25651901960372925},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.15555179119110107},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08268588781356812}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8159231543540955},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.750752329826355},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6290391683578491},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6146162748336792},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.6143218874931335},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5687161684036255},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5553250312805176},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5547585487365723},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5192908644676208},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4998054504394531},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4794665575027466},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4389117956161499},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.41334858536720276},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2972690761089325},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.25651901960372925},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.15555179119110107},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08268588781356812},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/ipdps.2006.1639438","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:fraunhofer.de:N-43218","is_oa":false,"landing_page_url":"http://publica.fraunhofer.de/documents/N-43218.html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400801","display_name":"Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Fraunhofer EAS","raw_type":"Conference Paper"},{"id":"pmh:oai:publica.fraunhofer.de:publica/350949","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/350949","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1951832803","https://openalex.org/W2110911638","https://openalex.org/W2111828735","https://openalex.org/W4250486818"],"related_works":["https://openalex.org/W2269990635","https://openalex.org/W2159022270","https://openalex.org/W1603163876","https://openalex.org/W2133642747","https://openalex.org/W2085480040","https://openalex.org/W1831349210","https://openalex.org/W3149594966","https://openalex.org/W2955432270","https://openalex.org/W2133408453","https://openalex.org/W2214116896"],"abstract_inverted_index":{"The":[0],"increasing":[1],"complexity":[2],"of":[3,25,34,71,83],"embedded":[4],"digital":[5],"HW/SW":[6],"systems,":[7],"rising":[8],"chip":[9],"development":[10],"and":[11,14,22,37,49,87],"fabrication":[12],"costs,":[13],"a":[15,35,42,55,84],"shortened":[16],"time-to-market":[17],"require":[18],"system-level":[19],"design":[20,29,47],"methods":[21],"the":[23,32,68,80],"use":[24],"reconfigurable":[26,74],"architectures.":[27,75],"Our":[28],"method":[30],"concerns":[31],"modelling":[33,82],"system":[36],"its":[38,63,88],"HW":[39,85],"tasks":[40],"at":[41],"high":[43],"abstraction":[44],"level.":[45],"Using":[46],"patterns":[48],"macros,":[50],"our":[51],"library-based":[52],"approach":[53],"provides":[54],"consistent":[56],"flow":[57],"from":[58],"an":[59],"executable":[60],"specification":[61],"to":[62],"implementation.":[64],"These":[65],"templates":[66],"ease":[67],"efficient":[69],"application":[70],"partially":[72],"run-time":[73],"A":[76],"case":[77],"study":[78],"depicts":[79],"high-level":[81],"task":[86],"implementation":[89],"in":[90],"detail.":[91]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
