{"id":"https://openalex.org/W3150687897","doi":"https://doi.org/10.1109/ipdps.2006.1639388","title":"Scheduling of tasks with precedence delays and relative deadlines framework for time-optimal dynamic reconfiguration of FPGAs","display_name":"Scheduling of tasks with precedence delays and relative deadlines framework for time-optimal dynamic reconfiguration of FPGAs","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3150687897","doi":"https://doi.org/10.1109/ipdps.2006.1639388","mag":"3150687897"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2006.1639388","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639388","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"P. Sucha","orcid":null},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Sucha","raw_affiliation_strings":["Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH","institution_ids":["https://openalex.org/I52357470"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039174863","display_name":"Zden\u011bk Hanz\u00e1lek","orcid":"https://orcid.org/0000-0002-8135-1296"},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Z. Hanzalek","raw_affiliation_strings":["Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH","institution_ids":["https://openalex.org/I52357470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I52357470"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.38916409,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"220","issue":null,"first_page":"8 pp.","last_page":"8 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7857636213302612},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7694847583770752},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6228299140930176},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6155973076820374},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5984015464782715},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.5268791317939758},{"id":"https://openalex.org/keywords/job-shop-scheduling","display_name":"Job shop scheduling","score":0.5101981163024902},{"id":"https://openalex.org/keywords/branch-and-bound","display_name":"Branch and bound","score":0.5009927749633789},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.47386884689331055},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.46977323293685913},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.45876142382621765},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.43541455268859863},{"id":"https://openalex.org/keywords/dynamic-programming","display_name":"Dynamic programming","score":0.4262961745262146},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4214799702167511},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4129559397697449},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.2924952507019043},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2901153564453125},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2691038250923157},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22912749648094177},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1511673629283905}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7857636213302612},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7694847583770752},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6228299140930176},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6155973076820374},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5984015464782715},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.5268791317939758},{"id":"https://openalex.org/C55416958","wikidata":"https://www.wikidata.org/wiki/Q6206757","display_name":"Job shop scheduling","level":3,"score":0.5101981163024902},{"id":"https://openalex.org/C93693863","wikidata":"https://www.wikidata.org/wiki/Q897659","display_name":"Branch and bound","level":2,"score":0.5009927749633789},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.47386884689331055},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.46977323293685913},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.45876142382621765},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.43541455268859863},{"id":"https://openalex.org/C37404715","wikidata":"https://www.wikidata.org/wiki/Q380679","display_name":"Dynamic programming","level":2,"score":0.4262961745262146},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4214799702167511},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4129559397697449},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2924952507019043},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2901153564453125},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2691038250923157},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22912749648094177},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1511673629283905},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2006.1639388","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2006.1639388","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1693765438","https://openalex.org/W1819660368","https://openalex.org/W1903036498","https://openalex.org/W1990033420","https://openalex.org/W1994669411","https://openalex.org/W2003346537","https://openalex.org/W2014875556","https://openalex.org/W2024060531","https://openalex.org/W2046751732","https://openalex.org/W2086629796","https://openalex.org/W2097025565","https://openalex.org/W2099562728","https://openalex.org/W2103166562","https://openalex.org/W2128193809","https://openalex.org/W2140926207","https://openalex.org/W2142184646","https://openalex.org/W2145251660","https://openalex.org/W2146438496","https://openalex.org/W2147740236","https://openalex.org/W2158598102","https://openalex.org/W2161455936","https://openalex.org/W2163488242","https://openalex.org/W2166811255","https://openalex.org/W4236269389","https://openalex.org/W4242608849","https://openalex.org/W4253136065","https://openalex.org/W4255701709","https://openalex.org/W6680773106"],"related_works":["https://openalex.org/W2357657342","https://openalex.org/W2153432761","https://openalex.org/W1580144672","https://openalex.org/W2152623100","https://openalex.org/W2142042635","https://openalex.org/W1988127757","https://openalex.org/W1859124475","https://openalex.org/W2103296973","https://openalex.org/W2129047123","https://openalex.org/W1964654856"],"abstract_inverted_index":{"This":[0,78],"paper":[1],"is":[2,80,125,133,143],"motivated":[3],"by":[4,33,44,52],"existing":[5],"architectures":[6],"of":[7,75,96,105,157],"field":[8],"programmable":[9],"gate":[10],"arrays":[11],"(FPGAs).":[12],"To":[13],"facilitate":[14],"the":[15,56,62,67,72,76,84,111,118,140,154,158],"design":[16],"process":[17],"we":[18],"present":[19],"an":[20,45,90,107],"optimal":[21,108],"scheduling":[22],"algorithm":[23],"using":[24,127],"a":[25,146],"very":[26],"universal":[27],"framework,":[28],"where":[29,48],"tasks":[30,49],"are":[31,42,50,58],"constrained":[32],"precedence":[34,40],"delays":[35],"and":[36,93,99,113,139,148,160,162],"relative":[37],"deadlines.":[38],"The":[39,102,130],"relations":[41],"given":[43],"oriented":[46],"graph,":[47],"represented":[51],"nodes.":[53],"Edges":[54],"in":[55],"graph":[57],"related":[59],"either":[60],"to":[61,66,82],"minimum":[63],"time":[64,69],"or":[65],"maximum":[68],"elapsed":[70],"between":[71],"start":[73],"times":[74],"tasks.":[77],"framework":[79],"used":[81],"model":[83],"runtime":[85],"dynamic":[86],"reconfiguration,":[87],"synchronization":[88],"with":[89],"on-chip":[91],"processor":[92],"simultaneous":[94],"availability":[95],"arithmetic":[97],"units":[98],"SRAM":[100],"memory.":[101],"NP-hard":[103],"problem":[104],"finding":[106],"schedule":[109],"satisfying":[110],"timing":[112],"resource":[114],"constraints":[115],"while":[116],"minimizing":[117],"makespan":[119],"C":[120],"<sub":[121],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[122],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">max</sub>":[123],",":[124],"solved":[126],"two":[128],"approaches.":[129],"first":[131],"one":[132,142],"based":[134],"on":[135],"integer":[136],"linear":[137],"programming":[138],"second":[141],"implemented":[144],"as":[145],"branch":[147,161],"bound":[149,163],"algorithm.":[150],"Experimental":[151],"results":[152],"show":[153],"efficiency":[155],"comparison":[156],"ILP":[159],"solutions":[164]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}
