{"id":"https://openalex.org/W1792849551","doi":"https://doi.org/10.1109/ipdps.2004.1303118","title":"System-on-programmable-chip approach enabling online fine-grained 1D-placement","display_name":"System-on-programmable-chip approach enabling online fine-grained 1D-placement","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W1792849551","doi":"https://doi.org/10.1109/ipdps.2004.1303118","mag":"1792849551"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2004.1303118","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303118","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030056981","display_name":"Heiko Kalte","orcid":null},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"H. Kalte","raw_affiliation_strings":["Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Paderborn, Germany","Heinz Nixdorf Institute, Paderborn University, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]},{"raw_affiliation_string":"Heinz Nixdorf Institute, Paderborn University, Germany#TAB#","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028498307","display_name":"Mario Porrmann","orcid":"https://orcid.org/0000-0003-1005-5753"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Porrmann","raw_affiliation_strings":["Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Paderborn, Germany","Heinz Nixdorf Institute, Paderborn University, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]},{"raw_affiliation_string":"Heinz Nixdorf Institute, Paderborn University, Germany#TAB#","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043372144","display_name":"Ulrich R\u00fcckert","orcid":null},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"U. Ruckert","raw_affiliation_strings":["Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Paderborn, Germany","Heinz Nixdorf Institute, Paderborn University, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]},{"raw_affiliation_string":"Heinz Nixdorf Institute, Paderborn University, Germany#TAB#","institution_ids":["https://openalex.org/I206945453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030056981"],"corresponding_institution_ids":["https://openalex.org/I206945453"],"apc_list":null,"apc_paid":null,"fwci":5.2818,"has_fulltext":false,"cited_by_count":46,"citation_normalized_percentile":{"value":0.95584289,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"151","issue":null,"first_page":"141","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8894830346107483},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8655070662498474},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7677243947982788},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6106988191604614},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5297105312347412},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4842531383037567},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.45206746459007263},{"id":"https://openalex.org/keywords/system-integration","display_name":"System integration","score":0.42349737882614136},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4216204285621643},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.371423602104187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10866224765777588},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06490615010261536}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8894830346107483},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8655070662498474},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7677243947982788},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6106988191604614},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5297105312347412},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4842531383037567},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.45206746459007263},{"id":"https://openalex.org/C19527686","wikidata":"https://www.wikidata.org/wiki/Q1665453","display_name":"System integration","level":2,"score":0.42349737882614136},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4216204285621643},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.371423602104187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10866224765777588},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06490615010261536},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ipdps.2004.1303118","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303118","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:pub.librecat.org:2286356","is_oa":false,"landing_page_url":"https://pub.uni-bielefeld.de/record/2286356","pdf_url":null,"source":{"id":"https://openalex.org/S4306401671","display_name":"PUB \u2013 Publications at Bielefeld University (Bielefeld University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I20121455","host_organization_name":"Bielefeld University","host_organization_lineage":["https://openalex.org/I20121455"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Kalte H, Porrmann M, R\u00fcckert U. System-on-programmable-chip approach enabling online fine-grained 1D-placement. In:  <em>Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International</em>. 2004: 141.","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W186640888","https://openalex.org/W1489568789","https://openalex.org/W1491948222","https://openalex.org/W1528410398","https://openalex.org/W1535835247","https://openalex.org/W1553483971","https://openalex.org/W1562700712","https://openalex.org/W1576594927","https://openalex.org/W1651202782","https://openalex.org/W2012647556","https://openalex.org/W2116345141","https://openalex.org/W2118785102","https://openalex.org/W2133697335","https://openalex.org/W2155071901","https://openalex.org/W4248152213","https://openalex.org/W4285719527","https://openalex.org/W6631470888","https://openalex.org/W6633208539","https://openalex.org/W6637027292","https://openalex.org/W6677750074","https://openalex.org/W6679944874"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2361654132","https://openalex.org/W4249632163"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"The":[4],"increasing":[5],"logic":[6],"density":[7,56],"of":[8,18,26,33,42,53,64,78,104,151],"current":[9],"FPGAs":[10,28],"(field":[11],"programmable":[12,23],"gate":[13],"arrays)":[14],"enables":[15,61,147],"the":[16,30,43,51,62,96,123,134,142,148],"integration":[17,63,126],"whole":[19],"systems":[20,66],"on":[21,89,95,127],"one":[22],"chip.":[24],"Some":[25],"these":[27],"provide":[29],"additional":[31],"feature":[32],"partial":[34,58],"dynamic":[35,59,65,124],"reconfiguration,":[36],"which":[37],"permits":[38],"to":[39,71,133],"change":[40],"parts":[41,47],"device":[44],"while":[45],"other":[46],"keep":[48],"working.":[49],"Combining":[50],"features":[52],"system":[54,125],"level":[55],"and":[57,92,114],"reconfiguration":[60],"that":[67,107,137],"can":[68,108],"be":[69,109],"adopted":[70],"changing":[72],"demands":[73],"during":[74],"runtime.":[75],"A":[76],"lot":[77],"theoretical":[79],"work":[80],"in":[81],"this":[82],"challenging":[83],"research":[84],"area":[85],"has":[86],"been":[87],"done":[88],"efficiently":[90],"placing":[91],"scheduling":[93],"modules":[94,152],"FPGA":[97],"area.":[98],"However,":[99],"there":[100],"is":[101],"a":[102,118,157],"lack":[103],"applied":[105],"approaches":[106,136],"realized":[110],"by":[111],"existing":[112,135],"tools":[113],"FPGAs.":[115,130],"We":[116],"present":[117],"new,":[119],"realizable":[120],"approach":[121,146],"for":[122,141],"Xilinx":[128],"Virtex":[129],"In":[131],"contrast":[132],"consider":[138],"fixed":[139],"slots":[140],"module":[143],"placement,":[144],"our":[145],"fine-grained":[149],"placement":[150],"with":[153],"variable":[154],"width":[155],"along":[156],"horizontal":[158],"communication":[159],"infrastructure.":[160]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":7}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}