{"id":"https://openalex.org/W2119191999","doi":"https://doi.org/10.1109/ipdps.2004.1303114","title":"Forward-looking macro generation and relational placement during high level synthesis to FPGAs","display_name":"Forward-looking macro generation and relational placement during high level synthesis to FPGAs","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2119191999","doi":"https://doi.org/10.1109/ipdps.2004.1303114","mag":"2119191999"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2004.1303114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Renqiu Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Renqiu Huang","raw_affiliation_strings":["Digital Design Environment Lab, Department of ECECS, University of Cincinnati, Cincinnati, OH, USA","Dept. of ECECS, Cincinnati Univ., OH, USA"],"affiliations":[{"raw_affiliation_string":"Digital Design Environment Lab, Department of ECECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"Dept. of ECECS, Cincinnati Univ., OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040975645","display_name":"Ranga Vemuri","orcid":"https://orcid.org/0000-0002-4903-2746"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Vemuri","raw_affiliation_strings":["Digital Design Environment Lab, Department of ECECS, University of Cincinnati, Cincinnati, OH, USA","Dept. of ECECS, Cincinnati Univ., OH, USA"],"affiliations":[{"raw_affiliation_string":"Digital Design Environment Lab, Department of ECECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"Dept. of ECECS, Cincinnati Univ., OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63135867"],"apc_list":null,"apc_paid":null,"fwci":0.2649,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.57729439,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"139","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7753328084945679},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6982783675193787},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6505290269851685},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6398167014122009},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5718637108802795},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5667717456817627},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.51048743724823},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.47317245602607727},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4721619784832001},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.46913713216781616},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4615153968334198},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.44518065452575684},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44208836555480957},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4151158034801483},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3679910898208618},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.31532734632492065},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2513209879398346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2166668176651001},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2026158571243286},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11239185929298401}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7753328084945679},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6982783675193787},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6505290269851685},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6398167014122009},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5718637108802795},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5667717456817627},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.51048743724823},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.47317245602607727},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4721619784832001},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.46913713216781616},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4615153968334198},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.44518065452575684},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44208836555480957},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4151158034801483},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3679910898208618},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.31532734632492065},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2513209879398346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2166668176651001},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2026158571243286},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11239185929298401},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2004.1303114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1566178705","https://openalex.org/W2009083496","https://openalex.org/W2041210719","https://openalex.org/W2072400712","https://openalex.org/W2074601596","https://openalex.org/W2074799901","https://openalex.org/W2105076302","https://openalex.org/W2135010865","https://openalex.org/W2139697722","https://openalex.org/W2626746498","https://openalex.org/W4248717925","https://openalex.org/W6675804706"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2269990635","https://openalex.org/W2108242004","https://openalex.org/W4283730710","https://openalex.org/W2246407281","https://openalex.org/W1557016741","https://openalex.org/W2735446578","https://openalex.org/W2543290882","https://openalex.org/W2060022998","https://openalex.org/W2945560322"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Incorporating":[4],"physical":[5,70],"information":[6],"into":[7,64],"earlier":[8],"architectural":[9],"and":[10,27,69,120],"logic":[11],"synthesis":[12,39,100],"stages":[13],"is":[14],"highly":[15],"desirable":[16],"since":[17],"it":[18,93],"allows":[19],"more":[20],"realistic":[21],"exploration":[22],"of":[23,30,88,97],"the":[24,28,48,62,82,95],"design":[25],"space":[26],"generation":[29],"solutions":[31],"with":[32,94,128],"predictable":[33],"metrics.":[34],"We":[35,58,72,79],"present":[36],"a":[37,86,98],"forward-looking":[38],"methodology":[40,107],"in":[41,47,61,113,124],"which":[42],"we":[43],"weigh":[44],"all":[45],"nets":[46],"control":[49],"data":[50],"flow":[51],"graph":[52],"(CDFG)":[53],"according":[54],"to":[55,110],"their":[56],"criticality.":[57],"cluster":[59],"operations":[60],"CDFG":[63],"macros":[65],"while":[66],"satisfying":[67],"logical":[68],"constraints.":[71],"perform":[73],"relational":[74],"placement":[75],"on":[76],"these":[77],"macros.":[78],"have":[80],"evaluated":[81],"proposed":[83],"approach":[84],"using":[85],"set":[87],"benchmark":[89],"designs":[90],"by":[91],"comparing":[92],"results":[96,103],"traditional":[99],"flow.":[101],"The":[102],"show":[104],"that":[105],"our":[106],"achieves":[108],"up":[109],"26%":[111],"improvement":[112,123],"clock":[114],"frequency":[115],"without":[116],"any":[117],"area":[118],"overhead,":[119],"average":[121],"12.7%":[122],"critical":[125],"path":[126],"delay":[127],"no":[129],"or":[130],"little":[131],"place-and-route":[132],"time":[133],"overhead.":[134]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}