{"id":"https://openalex.org/W1724186368","doi":"https://doi.org/10.1109/ipdps.2003.1213479","title":"Architectural frameworks for MPP systems on a chip","display_name":"Architectural frameworks for MPP systems on a chip","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W1724186368","doi":"https://doi.org/10.1109/ipdps.2003.1213479","mag":"1724186368"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2003.1213479","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2003.1213479","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Parallel and Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062434121","display_name":"David Andrews","orcid":"https://orcid.org/0000-0003-1464-7107"},"institutions":[{"id":"https://openalex.org/I146416000","display_name":"University of Kansas","ror":"https://ror.org/001tmjg57","country_code":"US","type":"education","lineage":["https://openalex.org/I146416000"]},{"id":"https://openalex.org/I4210126846","display_name":"Information Technology Laboratory","ror":"https://ror.org/0440c3437","country_code":"US","type":"government","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065","https://openalex.org/I4210126846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Andrews","raw_affiliation_strings":["Information Technology and Telecommunications Center, University of Kansas, USA","Inf. Technol. & Telecommun. Center, Kansas Univ., Lawrence, KS, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information Technology and Telecommunications Center, University of Kansas, USA","institution_ids":["https://openalex.org/I146416000","https://openalex.org/I4210126846"]},{"raw_affiliation_string":"Inf. Technol. & Telecommun. Center, Kansas Univ., Lawrence, KS, USA","institution_ids":["https://openalex.org/I146416000"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111946679","display_name":"D. Niehaus","orcid":null},"institutions":[{"id":"https://openalex.org/I146416000","display_name":"University of Kansas","ror":"https://ror.org/001tmjg57","country_code":"US","type":"education","lineage":["https://openalex.org/I146416000"]},{"id":"https://openalex.org/I4210126846","display_name":"Information Technology Laboratory","ror":"https://ror.org/0440c3437","country_code":"US","type":"government","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065","https://openalex.org/I4210126846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Niehaus","raw_affiliation_strings":["Information Technology and Telecommunications Center, University of Kansas, USA","Inf. Technol. & Telecommun. Center, Kansas Univ., Lawrence, KS, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information Technology and Telecommunications Center, University of Kansas, USA","institution_ids":["https://openalex.org/I146416000","https://openalex.org/I4210126846"]},{"raw_affiliation_string":"Inf. Technol. & Telecommun. Center, Kansas Univ., Lawrence, KS, USA","institution_ids":["https://openalex.org/I146416000"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.0839083,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"8","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8223382830619812},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6166010499000549},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.6039494276046753},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5727309584617615},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.5222621560096741},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5046564340591431},{"id":"https://openalex.org/keywords/personalization","display_name":"Personalization","score":0.5008847713470459},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.4911451041698456},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4719226360321045},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.43397608399391174},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2304321527481079},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1319635510444641}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8223382830619812},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6166010499000549},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.6039494276046753},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5727309584617615},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.5222621560096741},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5046564340591431},{"id":"https://openalex.org/C183003079","wikidata":"https://www.wikidata.org/wiki/Q1000371","display_name":"Personalization","level":2,"score":0.5008847713470459},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.4911451041698456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4719226360321045},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.43397608399391174},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2304321527481079},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1319635510444641},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ipdps.2003.1213479","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2003.1213479","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Parallel and Distributed Processing Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.119.4672","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.119.4672","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ittc.ku.edu/~dandrews/files/mpp.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1562697215","https://openalex.org/W1832923603","https://openalex.org/W1905924673","https://openalex.org/W2006090396","https://openalex.org/W2109140921","https://openalex.org/W2112432448","https://openalex.org/W2127071675","https://openalex.org/W2130224785","https://openalex.org/W2131005318","https://openalex.org/W2132326021","https://openalex.org/W2144430894","https://openalex.org/W2152056423","https://openalex.org/W2160454978","https://openalex.org/W2166720067","https://openalex.org/W3138410304","https://openalex.org/W4234177455","https://openalex.org/W4238156748","https://openalex.org/W4249058798","https://openalex.org/W4249868603","https://openalex.org/W6676157856","https://openalex.org/W6684528936"],"related_works":["https://openalex.org/W2950520577","https://openalex.org/W1501159154","https://openalex.org/W74409296","https://openalex.org/W2003935582","https://openalex.org/W2567390125","https://openalex.org/W1554644772","https://openalex.org/W305742777","https://openalex.org/W2940653809","https://openalex.org/W2468095077","https://openalex.org/W2124295435"],"abstract_inverted_index":{"Advances":[0],"in":[1],"fabrication":[2],"techniques":[3],"are":[4],"now":[5],"enabling":[6],"new":[7,21],"hybrid":[8,89],"CPU/FFPGA":[9],"computing":[10],"resources":[11],"to":[12,87,95,99],"be":[13,40],"integrated":[14],"onto":[15],"a":[16,43,58,70,112],"single":[17],"chip.":[18],"While":[19],"these":[20],"hybrids":[22],"promise":[23],"significant":[24],"performance":[25],"increases":[26],"through":[27],"the":[28,53,63,83,101,108],"customization":[29],"of":[30,104,107],"massive":[31],"gate":[32],"level":[33,103],"parallelism,":[34],"their":[35],"full":[36],"potential":[37,106],"will":[38],"not":[39],"reached":[41],"until":[42],"suitable":[44],"computational":[45,54,93],"framework":[46,55],"has":[47],"been":[48],"developed.":[49],"We":[50],"believe":[51],"that":[52,61],"should":[56],"provide":[57],"unified":[59],"model":[60,73,86],"brings":[62],"FPGA":[64,92],"and":[65,91,114],"CPU":[66,90],"based":[67],"components":[68,94],"under":[69],"common":[71],"programming":[72,85,116],"for":[74],"MPP":[75,102],"developers.":[76],"In":[77],"this":[78],"paper,":[79],"we":[80],"discuss":[81],"extending":[82],"thread":[84],"support":[88],"allow":[96],"systems":[97],"programmers":[98],"access":[100],"parallelism":[105],"FPGA,":[109],"but":[110],"within":[111],"familiar":[113],"understood":[115],"model.":[117]},"counts_by_year":[{"year":2015,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
