{"id":"https://openalex.org/W1863888138","doi":"https://doi.org/10.1109/ipdps.2003.1213224","title":"Parallel direct solution of linear equations on FPGA-based machines","display_name":"Parallel direct solution of linear equations on FPGA-based machines","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W1863888138","doi":"https://doi.org/10.1109/ipdps.2003.1213224","mag":"1863888138"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2003.1213224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2003.1213224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Parallel and Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100431602","display_name":"Xiaofang Wang","orcid":"https://orcid.org/0000-0002-5603-6411"},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xiaofang Wang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076762145","display_name":"Sotirios G. Ziavras","orcid":"https://orcid.org/0000-0002-3764-1528"},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.G. Ziavras","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100431602"],"corresponding_institution_ids":["https://openalex.org/I118118575"],"apc_list":null,"apc_paid":null,"fwci":3.7048,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.92548253,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"8","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7909921407699585},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7587100267410278},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7460524439811707},{"id":"https://openalex.org/keywords/factorization","display_name":"Factorization","score":0.6332911252975464},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6052794456481934},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5636667013168335},{"id":"https://openalex.org/keywords/lu-decomposition","display_name":"LU decomposition","score":0.48272082209587097},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.466092973947525},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.43082353472709656},{"id":"https://openalex.org/keywords/linear-system","display_name":"Linear system","score":0.41635024547576904},{"id":"https://openalex.org/keywords/matrix-decomposition","display_name":"Matrix decomposition","score":0.38286924362182617},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.33080849051475525},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3183375895023346},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24551421403884888},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15762478113174438}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7909921407699585},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7587100267410278},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7460524439811707},{"id":"https://openalex.org/C187834632","wikidata":"https://www.wikidata.org/wiki/Q188804","display_name":"Factorization","level":2,"score":0.6332911252975464},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6052794456481934},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5636667013168335},{"id":"https://openalex.org/C123213974","wikidata":"https://www.wikidata.org/wiki/Q833089","display_name":"LU decomposition","level":4,"score":0.48272082209587097},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.466092973947525},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.43082353472709656},{"id":"https://openalex.org/C6802819","wikidata":"https://www.wikidata.org/wiki/Q1072174","display_name":"Linear system","level":2,"score":0.41635024547576904},{"id":"https://openalex.org/C42355184","wikidata":"https://www.wikidata.org/wiki/Q1361088","display_name":"Matrix decomposition","level":3,"score":0.38286924362182617},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.33080849051475525},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3183375895023346},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24551421403884888},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15762478113174438},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C158693339","wikidata":"https://www.wikidata.org/wiki/Q190524","display_name":"Eigenvalues and eigenvectors","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ipdps.2003.1213224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2003.1213224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Parallel and Distributed Processing Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.10.7671","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.7671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://web.njit.edu/~ziavras/ZIAVRAS-02-WPDRTS-07.PDF","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W132603005","https://openalex.org/W605663379","https://openalex.org/W1512243664","https://openalex.org/W1595904496","https://openalex.org/W2052602889","https://openalex.org/W2110704067","https://openalex.org/W2115294662","https://openalex.org/W2119084939","https://openalex.org/W2125019445","https://openalex.org/W2168393172","https://openalex.org/W2169750514","https://openalex.org/W2249034827","https://openalex.org/W6684581351"],"related_works":["https://openalex.org/W2766762530","https://openalex.org/W119752240","https://openalex.org/W2602301532","https://openalex.org/W1988437637","https://openalex.org/W1977700955","https://openalex.org/W4388311419","https://openalex.org/W1973739845","https://openalex.org/W2127054029","https://openalex.org/W2060455298","https://openalex.org/W2366261058"],"abstract_inverted_index":{"The":[0],"efficient":[1],"solution":[2],"of":[3,6,33,44,53,71,85,108],"large":[4],"systems":[5],"linear":[7],"equations":[8],"represented":[9],"by":[10,20],"sparse":[11],"matrices":[12],"appears":[13],"in":[14],"many":[15,60],"tasks.":[16],"LU":[17,76,96],"factorization":[18,77,97],"followed":[19],"backward":[21],"and":[22,69],"forward":[23],"substitutions":[24],"is":[25,98],"widely":[26],"used":[27],"for":[28,62,75,95],"this":[29,34],"purpose.":[30],"Parallel":[31],"implementations":[32],"computation-intensive":[35],"process":[36],"are":[37],"limited":[38],"primarily":[39],"to":[40,100],"supercomputers.":[41],"New":[42],"generations":[43],"field-programmable":[45],"gate":[46],"array":[47],"(FPGA)":[48],"technologies":[49],"enable":[50],"the":[51,67,106],"implementation":[52,70],"system-on-a-programmable-chip":[54],"(SOPC)":[55],"computing":[56],"platforms":[57],"that":[58],"provide":[59],"opportunities":[61],"configurable":[63],"computing.":[64],"We":[65],"present":[66],"design":[68],"a":[72,86],"parallel":[73,91],"machine":[74],"on":[78],"an":[79],"SOPC":[80],"board,":[81],"using":[82],"multiple":[83],"instances":[84],"soft":[87],"processor.":[88],"A":[89],"highly":[90],"block-diagonal-bordered":[92],"(BDB)":[93],"algorithm":[94],"mapped":[99],"our":[101,109],"multiprocessor.":[102],"Our":[103],"results":[104],"prove":[105],"viability":[107],"FPGA-based":[110],"approach.":[111]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}