{"id":"https://openalex.org/W2760618420","doi":"https://doi.org/10.1109/iolts.2017.8046171","title":"Controller augmentation and test point insertion at RTL for concurrent operational unit testing","display_name":"Controller augmentation and test point insertion at RTL for concurrent operational unit testing","publication_year":2017,"publication_date":"2017-07-01","ids":{"openalex":"https://openalex.org/W2760618420","doi":"https://doi.org/10.1109/iolts.2017.8046171","mag":"2760618420"},"language":"en","primary_location":{"id":"doi:10.1109/iolts.2017.8046171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2017.8046171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113865938","display_name":"Toshinori Hosokawa","orcid":null},"institutions":[{"id":"https://openalex.org/I104946051","display_name":"Nihon University","ror":"https://ror.org/05jk51a88","country_code":"JP","type":"education","lineage":["https://openalex.org/I104946051"]},{"id":"https://openalex.org/I52706244","display_name":"College of Industrial Technology","ror":"https://ror.org/054a9s036","country_code":"JP","type":"education","lineage":["https://openalex.org/I52706244"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori Hosokawa","raw_affiliation_strings":["College of Industrial Technology, Nihon University, Chiba, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Industrial Technology, Nihon University, Chiba, JAPAN","institution_ids":["https://openalex.org/I104946051","https://openalex.org/I52706244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112723413","display_name":"Shun Takeda","orcid":null},"institutions":[{"id":"https://openalex.org/I104946051","display_name":"Nihon University","ror":"https://ror.org/05jk51a88","country_code":"JP","type":"education","lineage":["https://openalex.org/I104946051"]},{"id":"https://openalex.org/I52706244","display_name":"College of Industrial Technology","ror":"https://ror.org/054a9s036","country_code":"JP","type":"education","lineage":["https://openalex.org/I52706244"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shun Takeda","raw_affiliation_strings":["Graduate School of Industrial Technology, Nihon University, Chiba, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Industrial Technology, Nihon University, Chiba, JAPAN","institution_ids":["https://openalex.org/I104946051","https://openalex.org/I52706244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015411968","display_name":"Hiroshi Yamazaki","orcid":"https://orcid.org/0000-0001-9434-2957"},"institutions":[{"id":"https://openalex.org/I104946051","display_name":"Nihon University","ror":"https://ror.org/05jk51a88","country_code":"JP","type":"education","lineage":["https://openalex.org/I104946051"]},{"id":"https://openalex.org/I52706244","display_name":"College of Industrial Technology","ror":"https://ror.org/054a9s036","country_code":"JP","type":"education","lineage":["https://openalex.org/I52706244"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroshi Yamazaki","raw_affiliation_strings":["College of Industrial Technology, Nihon University, Chiba, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Industrial Technology, Nihon University, Chiba, JAPAN","institution_ids":["https://openalex.org/I104946051","https://openalex.org/I52706244"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101029241","display_name":"Masayoshi Yoshimura","orcid":null},"institutions":[{"id":"https://openalex.org/I168356945","display_name":"Kyoto Sangyo University","ror":"https://ror.org/05t70xh16","country_code":"JP","type":"education","lineage":["https://openalex.org/I168356945"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masayoshi Yoshimura","raw_affiliation_strings":["Faculty of Computer Science and Engineering, Kyoto Sangyo University, Kyoto, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Computer Science and Engineering, Kyoto Sangyo University, Kyoto, JAPAN","institution_ids":["https://openalex.org/I168356945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3804,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.51571206,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"16","issue":null,"first_page":"17","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.7353700399398804},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6894779801368713},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.649232029914856},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5932217836380005},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.578626275062561},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5507930517196655},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.48759594559669495},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.48738032579421997},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.48171764612197876},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.45627087354660034},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4561149775981903},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.41704100370407104},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4165083169937134},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4128752648830414},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.38188523054122925},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.27461516857147217},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2170409858226776},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09297505021095276}],"concepts":[{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.7353700399398804},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6894779801368713},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.649232029914856},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5932217836380005},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.578626275062561},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5507930517196655},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.48759594559669495},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.48738032579421997},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.48171764612197876},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.45627087354660034},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4561149775981903},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.41704100370407104},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4165083169937134},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4128752648830414},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.38188523054122925},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27461516857147217},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2170409858226776},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09297505021095276},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iolts.2017.8046171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2017.8046171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1549616995","https://openalex.org/W1882684267","https://openalex.org/W2097282779","https://openalex.org/W2110019537","https://openalex.org/W2118133071","https://openalex.org/W2124628240","https://openalex.org/W2124684331","https://openalex.org/W2138251715","https://openalex.org/W2151526282","https://openalex.org/W2162543434","https://openalex.org/W6632829180","https://openalex.org/W6678608646"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2154529098","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314","https://openalex.org/W2146381271","https://openalex.org/W2105858357","https://openalex.org/W2989178840"],"abstract_inverted_index":{"Test":[0,95],"point":[1,33,64],"insertion":[2,65],"methods":[3],"to":[4,30,47,55,82],"reduce":[5],"the":[6,18,26,69,120],"number":[7,121],"of":[8,20,28,87,122],"test":[9,32,63,75,80,123],"patterns":[10,124],"at":[11,43],"register":[12,44,81],"transfer":[13,45],"level":[14,46],"are":[15],"required":[16],"for":[17,105],"adaptability":[19],"traditional":[21],"VLSI":[22],"design":[23],"flows":[24],"and":[25,66,77,84],"reduction":[27],"time":[29],"search":[31],"locations.":[34],"In":[35],"this":[36],"paper,":[37],"we":[38],"propose":[39],"a":[40,92],"design-for-testability":[41,71],"method":[42,72,118],"enable":[48],"operational":[49,89,106],"units":[50],"as":[51,53],"many":[52],"possible":[54],"be":[56],"concurrently":[57],"tested":[58],"in":[59,91],"scan":[60],"testing.":[61],"Using":[62],"controller":[67],"augmentation,":[68],"proposed":[70,117],"allocates":[73],"input":[74],"registers":[76],"an":[78,85],"output":[79,86],"inputs":[83],"each":[88],"unit":[90],"data-path,":[93],"respectively.":[94],"compaction":[96],"efficiency":[97],"becomes":[98],"high":[99],"by":[100,125],"enabling":[101],"effective":[102],"concurrent":[103],"testing":[104],"units.":[107],"Experimental":[108],"results":[109],"on":[110,131],"high-level":[111],"benchmark":[112],"circuits":[113],"show":[114],"that":[115],"our":[116],"reduced":[119],"20%":[126],"with":[127],"6.5%":[128],"area":[129],"overhead":[130],"average.":[132]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
