{"id":"https://openalex.org/W2539059759","doi":"https://doi.org/10.1109/iolts.2016.7604687","title":"Tackling long duration transients in sequential logic","display_name":"Tackling long duration transients in sequential logic","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2539059759","doi":"https://doi.org/10.1109/iolts.2016.7604687","mag":"2539059759"},"language":"en","primary_location":{"id":"doi:10.1109/iolts.2016.7604687","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2016.7604687","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085639767","display_name":"Erol Koser","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Erol Koser","raw_affiliation_strings":["Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, M\u00fcnchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005732789","display_name":"Walter Stechele","orcid":"https://orcid.org/0000-0002-7455-8483"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Walter Stechele","raw_affiliation_strings":["Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, M\u00fcnchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5085639767"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58812424,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"137","last_page":"142"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6222620606422424},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6199661493301392},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6181872487068176},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4928431510925293},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.47373878955841064},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4443104565143585},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4245515465736389},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39103981852531433},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38576167821884155},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3376971483230591},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24674808979034424},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16129624843597412}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6222620606422424},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6199661493301392},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6181872487068176},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4928431510925293},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.47373878955841064},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4443104565143585},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4245515465736389},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39103981852531433},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38576167821884155},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3376971483230591},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24674808979034424},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16129624843597412},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iolts.2016.7604687","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2016.7604687","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","score":0.8199999928474426,"display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1493708942","https://openalex.org/W1945335772","https://openalex.org/W1965660246","https://openalex.org/W1967569723","https://openalex.org/W2018976752","https://openalex.org/W2025340565","https://openalex.org/W2045845641","https://openalex.org/W2058424176","https://openalex.org/W2073772173","https://openalex.org/W2096692505","https://openalex.org/W2098247453","https://openalex.org/W2104677471","https://openalex.org/W2127658067","https://openalex.org/W2134253040","https://openalex.org/W2151491839","https://openalex.org/W2152652532","https://openalex.org/W2153922221","https://openalex.org/W2158359146","https://openalex.org/W2169213530","https://openalex.org/W2178304595","https://openalex.org/W2541775499","https://openalex.org/W2979917050","https://openalex.org/W4229525459","https://openalex.org/W4236432903","https://openalex.org/W6662007798"],"related_works":["https://openalex.org/W2128496560","https://openalex.org/W4248162147","https://openalex.org/W2095349217","https://openalex.org/W4388212011","https://openalex.org/W2126951255","https://openalex.org/W2052802431","https://openalex.org/W3208012256","https://openalex.org/W2027462780","https://openalex.org/W2074526596","https://openalex.org/W4242010157"],"abstract_inverted_index":{"Single":[0],"Event":[1],"Transients":[2,63],"(SETs)":[3],"in":[4,13,22,38,56],"combinational":[5],"logic":[6],"remain":[7],"to":[8,24,52,76,85,142],"be":[9],"an":[10,130,153],"important":[11],"topic":[12],"the":[14,25,31,43,57,90],"reliability":[15],"domain.":[16],"SETs":[17,48],"were":[18],"traditionally":[19],"relatively":[20],"short":[21],"comparison":[23],"clock":[26,54],"period.":[27],"The":[28,105,118,126],"majority":[29],"of":[30,89,110,133,139],"countermeasures":[32],"utilizes":[33,120],"this":[34],"property.":[35],"However,":[36],"advances":[37],"technology":[39],"scaling":[40],"will":[41],"reverse":[42],"ratio.":[44],"Investigations":[45],"show":[46],"that":[47,99],"may":[49],"last":[50],"up":[51],"multiple":[53],"cycles":[55],"future.":[58],"So":[59],"called":[60],"Long":[61],"Duration":[62],"(LDTs)":[64],"corrupt":[65],"almost":[66],"all":[67],"available":[68],"countermeasures.":[69],"This":[70],"work":[71],"presents":[72],"a":[73,121,136,143],"new":[74,94],"methodology":[75],"tackle":[77],"LDTs.":[78],"Dual":[79],"Modular":[80],"Redundancy":[81],"(DMR)":[82],"is":[83,97,107],"used":[84],"detect":[86],"any":[87],"corruption":[88],"application":[91],"logic.":[92],"A":[93],"micro-rollback":[95],"scheme":[96,119],"introduced,":[98],"expands":[100],"DMR-Architectures":[101],"with":[102,156],"correction":[103,157],"capabilities.":[104],"concept":[106],"also":[108],"capable":[109],"handling":[111],"single":[112],"event":[113],"upsets":[114],"and":[115,135,148,162],"timing":[116],"violations.":[117],"newly":[122],"designed":[123],"History":[124,127],"Cell.":[125],"Cell":[128],"introduces":[129],"area":[131],"overhead":[132,138],"74%":[134],"power":[137,149],"106%":[140],"compared":[141],"standard":[144],"cell":[145],"D-flip-flop.":[146],"Area":[147],"overheads":[150],"for":[151],"expanding":[152],"existing":[154],"DMR-Architecture":[155],"capabilities":[158],"are":[159],"approximately":[160],"24%":[161],"28%,":[163],"respectively.":[164]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
