{"id":"https://openalex.org/W2051928092","doi":"https://doi.org/10.1109/iolts.2012.6313842","title":"The influence of clock-gating on NBTI-induced delay degradation","display_name":"The influence of clock-gating on NBTI-induced delay degradation","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W2051928092","doi":"https://doi.org/10.1109/iolts.2012.6313842","mag":"2051928092"},"language":"en","primary_location":{"id":"doi:10.1109/iolts.2012.6313842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2012.6313842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018103265","display_name":"Jackson Pachito","orcid":null},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I71503853","display_name":"University of Algarve","ror":"https://ror.org/014g34x36","country_code":"PT","type":"education","lineage":["https://openalex.org/I71503853"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Pachito","raw_affiliation_strings":["INESC-ID Lisbon, University of Algarve, Faro, Portugal","Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, University of Algarve, Faro, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I71503853"]},{"raw_affiliation_string":"Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal#TAB#","institution_ids":["https://openalex.org/I71503853"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109967328","display_name":"C. V. Martins","orcid":null},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I71503853","display_name":"University of Algarve","ror":"https://ror.org/014g34x36","country_code":"PT","type":"education","lineage":["https://openalex.org/I71503853"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"C. V. Martins","raw_affiliation_strings":["INESC-ID Lisbon, University of Algarve, Faro, Portugal","Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, University of Algarve, Faro, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I71503853"]},{"raw_affiliation_string":"Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal#TAB#","institution_ids":["https://openalex.org/I71503853"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018531470","display_name":"J. Semi\u00e3o","orcid":"https://orcid.org/0000-0002-7667-7910"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I71503853","display_name":"University of Algarve","ror":"https://ror.org/014g34x36","country_code":"PT","type":"education","lineage":["https://openalex.org/I71503853"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Semiao","raw_affiliation_strings":["INESC-ID Lisbon, University of Algarve, Faro, Portugal","Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, University of Algarve, Faro, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I71503853"]},{"raw_affiliation_string":"Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal#TAB#","institution_ids":["https://openalex.org/I71503853"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047445549","display_name":"Marcelino Santos","orcid":"https://orcid.org/0000-0002-2091-1165"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"M. Santos","raw_affiliation_strings":["INESC-ID Lisbon, UTL Corporation, Lisboa, Portugal","INESC-ID Lisbon / IST-UTL, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, UTL Corporation, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"INESC-ID Lisbon / IST-UTL, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039557784","display_name":"I.C. Teixeira","orcid":"https://orcid.org/0000-0002-2642-5619"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"I. C. Teixeira","raw_affiliation_strings":["INESC-ID Lisbon, UTL Corporation, Lisboa, Portugal","INESC-ID Lisbon / IST-UTL, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, UTL Corporation, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"INESC-ID Lisbon / IST-UTL, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058862498","display_name":"J.P. Teixeira","orcid":"https://orcid.org/0000-0002-0379-6257"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. P. Teixeira","raw_affiliation_strings":["INESC-ID Lisbon, UTL Corporation, Lisboa, Portugal","INESC-ID Lisbon / IST-UTL, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, UTL Corporation, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"INESC-ID Lisbon / IST-UTL, Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"61","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7639442682266235},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7594436407089233},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6681832671165466},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6209078431129456},{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.6196288466453552},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.6165226101875305},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5880493521690369},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5674937963485718},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4850999116897583},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47843506932258606},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.46329036355018616},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.39500266313552856},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3381827771663666},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.33698830008506775},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2766924500465393},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.2661301791667938},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25703829526901245},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2400137484073639}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7639442682266235},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7594436407089233},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6681832671165466},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6209078431129456},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.6196288466453552},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.6165226101875305},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5880493521690369},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5674937963485718},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4850999116897583},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47843506932258606},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.46329036355018616},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.39500266313552856},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3381827771663666},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.33698830008506775},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2766924500465393},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.2661301791667938},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25703829526901245},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2400137484073639},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iolts.2012.6313842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2012.6313842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6899999976158142,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1991891926","https://openalex.org/W2091472688","https://openalex.org/W2102488630","https://openalex.org/W2102729267","https://openalex.org/W2118214977","https://openalex.org/W2120802493","https://openalex.org/W2127128585","https://openalex.org/W2141565132","https://openalex.org/W2146518537","https://openalex.org/W2147091592","https://openalex.org/W2148954445","https://openalex.org/W2151802820","https://openalex.org/W2170333286","https://openalex.org/W2171805009","https://openalex.org/W2253047948","https://openalex.org/W4237900519","https://openalex.org/W6677500415"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2117814846","https://openalex.org/W2308963021","https://openalex.org/W2144282137","https://openalex.org/W2116514610","https://openalex.org/W2052455055","https://openalex.org/W2090237663","https://openalex.org/W2076992934","https://openalex.org/W4200240321","https://openalex.org/W2118167094"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"analysis":[4],"of":[5,8,15,52],"the":[6,13,25,90,94,104,122,127],"implications":[7],"clock":[9,87],"gating":[10,88],"techniques":[11],"on":[12],"increase":[14,40],"aging":[16],"degradations":[17,32,67],"in":[18,82,93,126,137],"new":[19],"node":[20],"digital":[21],"circuits.":[22],"NBTI":[23,70],"is":[24,61,109],"dominant":[26],"effect":[27],"that":[28,77,119],"cause":[29],"long-term":[30],"performance":[31,66,91,116],"over":[33,72],"time,":[34],"and":[35,54],"circuit":[36],"operating":[37,56],"conditions":[38],"may":[39],"significantly":[41],"these":[42],"degradations,":[43],"namely":[44],"with":[45,86,115],"high":[46],"power-supply":[47],"voltage":[48],"values,":[49],"signals'":[50],"probability":[51],"operation":[53],"low":[55],"frequencies.":[57],"A":[58],"proprietary":[59],"tool":[60],"used,":[62],"AgingCalc,":[63],"to":[64,99,110],"predict":[65],"caused":[68],"by":[69,78,103],"effects":[71],"time.":[73],"SPICE":[74],"simulations":[75],"show":[76],"reducing":[79],"signal":[80],"transitions":[81],"pipeline":[83,105],"circuits":[84],"implemented":[85],"techniques,":[89],"degradation":[92],"critical":[95],"paths":[96],"could":[97],"lead":[98],"delay":[100,123],"errors":[101],"captured":[102],"stages.":[106],"The":[107],"solution":[108],"replace":[111],"specific":[112],"flip-flops":[113],"(FF)":[114],"sensors'":[117],"FF,":[118],"allow":[120],"predicting":[121],"error":[124],"occurrence":[125],"pipeline.":[128],"Simulation":[129],"results":[130],"are":[131],"presented":[132],"for":[133],"five":[134],"case":[135],"studies":[136],"65":[138],"nm":[139],"CMOS":[140],"technology,":[141],"using":[142],"Berkeley":[143],"Predictive":[144],"Technology":[145],"Models":[146],"(PTM).":[147]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}