{"id":"https://openalex.org/W2070347956","doi":"https://doi.org/10.1109/iolts.2011.5994538","title":"An analytical model for the calculation of the Expected Miss Ratio in faulty caches","display_name":"An analytical model for the calculation of the Expected Miss Ratio in faulty caches","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2070347956","doi":"https://doi.org/10.1109/iolts.2011.5994538","mag":"2070347956"},"language":"en","primary_location":{"id":"doi:10.1109/iolts.2011.5994538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2011.5994538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 17th International On-Line Testing Symposium","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023312480","display_name":"Daniel S\u00e1nchez","orcid":"https://orcid.org/0000-0002-2453-2904"},"institutions":[{"id":"https://openalex.org/I80180929","display_name":"Universidad de Murcia","ror":"https://ror.org/03p3aeb86","country_code":"ES","type":"education","lineage":["https://openalex.org/I80180929"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Daniel Sanchez","raw_affiliation_strings":["Department of Computer Engineering, University of Murcia, Spain","Dept. of Computer Engineering University of Murcia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Murcia, Spain","institution_ids":["https://openalex.org/I80180929"]},{"raw_affiliation_string":"Dept. of Computer Engineering University of Murcia","institution_ids":["https://openalex.org/I80180929"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112557559","display_name":"Yiannakis Sazeides","orcid":null},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Yiannakis Sazeides","raw_affiliation_strings":["Department of Computer Science, University of Cyprus, Cyprus","Dept. of Computer Science University of Cyprus"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Cyprus, Cyprus","institution_ids":["https://openalex.org/I34771391"]},{"raw_affiliation_string":"Dept. of Computer Science University of Cyprus","institution_ids":["https://openalex.org/I34771391"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079508006","display_name":"Juan L. Arag\u00f3n","orcid":"https://orcid.org/0000-0002-4955-7235"},"institutions":[{"id":"https://openalex.org/I80180929","display_name":"Universidad de Murcia","ror":"https://ror.org/03p3aeb86","country_code":"ES","type":"education","lineage":["https://openalex.org/I80180929"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan L. Aragon","raw_affiliation_strings":["Department of Computer Engineering, University of Murcia, Spain","Dept. of Computer Engineering University of Murcia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Murcia, Spain","institution_ids":["https://openalex.org/I80180929"]},{"raw_affiliation_string":"Dept. of Computer Engineering University of Murcia","institution_ids":["https://openalex.org/I80180929"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070286319","display_name":"Jos\u00e9 M. Garc\u0131\u0301a","orcid":"https://orcid.org/0000-0002-6388-2835"},"institutions":[{"id":"https://openalex.org/I80180929","display_name":"Universidad de Murcia","ror":"https://ror.org/03p3aeb86","country_code":"ES","type":"education","lineage":["https://openalex.org/I80180929"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Joso M. Garcia","raw_affiliation_strings":["Department of Computer Engineering, University of Murcia, Spain","Dept. of Computer Engineering University of Murcia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Murcia, Spain","institution_ids":["https://openalex.org/I80180929"]},{"raw_affiliation_string":"Dept. of Computer Engineering University of Murcia","institution_ids":["https://openalex.org/I80180929"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.79,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.83562593,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"33","issue":null,"first_page":"252","last_page":"257"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.840928852558136},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7725058197975159},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7187871932983398},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6277551054954529},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.578376293182373},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.55618816614151},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5000019073486328},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4681929051876068},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.46596673130989075},{"id":"https://openalex.org/keywords/failure-rate","display_name":"Failure rate","score":0.43908393383026123},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3749956488609314},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.373431921005249},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12371364235877991},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.08124610781669617}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.840928852558136},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7725058197975159},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7187871932983398},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6277551054954529},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.578376293182373},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.55618816614151},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5000019073486328},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4681929051876068},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.46596673130989075},{"id":"https://openalex.org/C163164238","wikidata":"https://www.wikidata.org/wiki/Q2737027","display_name":"Failure rate","level":2,"score":0.43908393383026123},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3749956488609314},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.373431921005249},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12371364235877991},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.08124610781669617},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iolts.2011.5994538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2011.5994538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 17th International On-Line Testing Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.348.4066","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.348.4066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ditec.um.es/~jlaragon/papers/sanchez_IOLTS11.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1702767802","https://openalex.org/W1981044614","https://openalex.org/W2004423835","https://openalex.org/W2053828888","https://openalex.org/W2056971515","https://openalex.org/W2059315682","https://openalex.org/W2074088899","https://openalex.org/W2079163915","https://openalex.org/W2095267534","https://openalex.org/W2110283673","https://openalex.org/W2111026284","https://openalex.org/W2117648153","https://openalex.org/W2120635877","https://openalex.org/W2125263803","https://openalex.org/W2125830979","https://openalex.org/W2135719553","https://openalex.org/W2155166680","https://openalex.org/W2160401437","https://openalex.org/W2161197576","https://openalex.org/W2162707747","https://openalex.org/W2164264749","https://openalex.org/W2168101540","https://openalex.org/W2170874491","https://openalex.org/W4238002809","https://openalex.org/W4242760028","https://openalex.org/W4255298641","https://openalex.org/W6645548519"],"related_works":["https://openalex.org/W2147122795","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W2167303720","https://openalex.org/W2268996566","https://openalex.org/W2109715593","https://openalex.org/W3161817247","https://openalex.org/W2012518269","https://openalex.org/W2068309140","https://openalex.org/W4239937081"],"abstract_inverted_index":{"Technology":[0],"scaling":[1],"improvement":[2],"is":[3,23,54,75,82,93,127,166,187],"affecting":[4],"the":[5,30,60,102,107,132,144,176,182,192],"reliability":[6,52],"of":[7,32,65,104,117,134,161,184,194],"ICs":[8],"due":[9,67],"to":[10,42,48,68,130,168],"increases":[11],"in":[12,80,106,121,151],"static":[13],"and":[14,35,90,147,172,196],"dynamic":[15],"variations":[16],"as":[17,19],"well":[18],"wear-out":[20],"failures.":[21],"This":[22],"particularly":[24],"true":[25],"for":[26,58,143,175],"caches":[27],"that":[28,81,181],"dominate":[29],"area":[31],"modern":[33],"processors":[34],"are":[36,112],"built":[37],"with":[38],"minimum-sized,":[39],"but":[40],"prone":[41],"failure,":[43],"SRAM":[44],"cells.":[45],"Our":[46],"attempt":[47],"address":[49],"this":[50,152,185],"cache":[51,63,118,148,200],"challenge":[53],"an":[55,83,88],"analytical":[56],"model":[57,74,85,110,126],"determining":[59],"implications":[61],"on":[62],"miss-rate":[64,119],"block-disabling":[66],"random":[69,136,162],"cell":[70],"failure.":[71],"The":[72,109,125,140],"proposed":[73],"distinct":[76],"from":[77,101],"previous":[78,96],"work":[79],"exact":[84],"rather":[86],"than":[87,95],"approximation":[89],"yet":[91],"it":[92],"simpler":[94],"work.":[97],"Its":[98],"simplicity":[99],"stems":[100],"lack":[103],"fault-maps":[105],"analysis.":[108],"capabilities":[111],"illustrated":[113],"through":[114],"a":[115,135,154,157,188],"study":[116],"trends":[120],"future":[122],"technology":[123],"nodes.":[124],"also":[128],"used":[129,150],"determine":[131],"accuracy":[133],"fault":[137,163],"map":[138],"methodology.":[139],"analysis":[141],"reveals,":[142],"assumptions,":[145],"programs":[146],"configuration":[149],"study,":[153],"surprising":[155],"result:":[156],"relative":[158],"small":[159],"number":[160,193],"maps,":[164],"100\u20131000,":[165],"sufficient":[167],"obtain":[169],"accurate":[170],"mean":[171],"standard-deviation":[173],"values":[174],"miss-rate.":[177],"Additional":[178],"investigation":[179],"revealed":[180],"cause":[183],"behavior":[186],"high":[189],"correlation":[190],"between":[191,199],"accesses":[195],"access":[197],"distribution":[198],"sets.":[201]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
