{"id":"https://openalex.org/W1999076355","doi":"https://doi.org/10.1109/iolts.2010.5560188","title":"Robust detection of soft errors using delayed capture methodology","display_name":"Robust detection of soft errors using delayed capture methodology","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W1999076355","doi":"https://doi.org/10.1109/iolts.2010.5560188","mag":"1999076355"},"language":"en","primary_location":{"id":"doi:10.1109/iolts.2010.5560188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2010.5560188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE 16th International On-Line Testing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112005511","display_name":"V Prasanth","orcid":null},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]},{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"V Prasanth","raw_affiliation_strings":["Computer Design and Test Laboratory, Indian Institute of Science, Bangalore, India","Texas Instruments (India) Private Limited, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Computer Design and Test Laboratory, Indian Institute of Science, Bangalore, India","institution_ids":["https://openalex.org/I59270414"]},{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Computer Design and Test Laboratory, Indian Institute of Science, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Computer Design and Test Laboratory, Indian Institute of Science, Bangalore, India","institution_ids":["https://openalex.org/I59270414"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028519358","display_name":"Rubin Parekhji","orcid":"https://orcid.org/0009-0000-6625-2786"},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rubin Parekhji","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112005511"],"corresponding_institution_ids":["https://openalex.org/I4210109535","https://openalex.org/I59270414"],"apc_list":null,"apc_paid":null,"fwci":0.5773,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.70199998,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"277","last_page":"282"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7218509912490845},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.681912362575531},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.654296338558197},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6183027029037476},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.5489795207977295},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5267110466957092},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5186892747879028},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5142159461975098},{"id":"https://openalex.org/keywords/parity-bit","display_name":"Parity bit","score":0.47376587986946106},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.45746830105781555},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.45745575428009033},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.43943724036216736},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.31203681230545044},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26777976751327515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2244272232055664},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.151108980178833}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7218509912490845},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.681912362575531},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.654296338558197},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6183027029037476},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.5489795207977295},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5267110466957092},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5186892747879028},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5142159461975098},{"id":"https://openalex.org/C131521367","wikidata":"https://www.wikidata.org/wiki/Q625502","display_name":"Parity bit","level":2,"score":0.47376587986946106},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.45746830105781555},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.45745575428009033},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.43943724036216736},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.31203681230545044},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26777976751327515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2244272232055664},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.151108980178833},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iolts.2010.5560188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2010.5560188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE 16th International On-Line Testing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W160422864","https://openalex.org/W1940286823","https://openalex.org/W1979668030","https://openalex.org/W1981194937","https://openalex.org/W2000379092","https://openalex.org/W2023856022","https://openalex.org/W2052153312","https://openalex.org/W2054593687","https://openalex.org/W2078719641","https://openalex.org/W2099569658","https://openalex.org/W2104677471","https://openalex.org/W2128248970","https://openalex.org/W2142358791","https://openalex.org/W2143557070","https://openalex.org/W2154207847","https://openalex.org/W2161033118","https://openalex.org/W2162465831","https://openalex.org/W2169213530","https://openalex.org/W3149410719","https://openalex.org/W4235118605","https://openalex.org/W4236432903","https://openalex.org/W6606583247","https://openalex.org/W6663529649","https://openalex.org/W6995950621","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W2531550288","https://openalex.org/W2149041233","https://openalex.org/W2171347834","https://openalex.org/W2066042903","https://openalex.org/W2090290079","https://openalex.org/W3040935927","https://openalex.org/W1993206924","https://openalex.org/W2066664769","https://openalex.org/W2168546702","https://openalex.org/W2518564956"],"abstract_inverted_index":{"With":[0],"the":[1,9,30,37,50,78,81,86,89,92,100,108],"scaling":[2],"of":[3,11,26,52,80,102,107],"technology":[4],"node":[5],"and":[6,58,67,83,94],"voltage":[7],"levels,":[8],"susceptibility":[10],"logic":[12,32],"to":[13,23,48,98],"soft":[14,27,53,103],"errors":[15,28,54],"is":[16,20,46,69,96,110],"increasing.":[17],"Hence":[18],"it":[19],"very":[21],"important":[22],"take":[24],"care":[25],"in":[29,36,55],"combinational":[31,57],"along":[33],"with":[34],"those":[35],"sequential":[38,59],"elements.":[39],"In":[40,61],"this":[41,62],"paper,":[42],"a":[43],"novel":[44],"method":[45],"proposed":[47],"detect":[49,99],"presence":[51,101],"both":[56],"logic.":[60],"method,":[63],"flip-flops":[64,82],"are":[65],"grouped":[66],"parity":[68,90],"computed":[70],"for":[71],"each":[72],"group":[73],"twice":[74],"-":[75],"once":[76],"at":[77,85,91],"input":[79],"next":[84],"output.":[87],"Later,":[88],"inputs":[93],"outputs":[95],"compared":[97],"errors.":[104],"The":[105],"effectiveness":[106],"technique":[109],"shown":[111],"through":[112],"experimental":[113],"results.":[114]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
