{"id":"https://openalex.org/W2084345978","doi":"https://doi.org/10.1109/iolts.2009.5196016","title":"Analysis of the extra delay on interconnects caused by resistive opens and shorts","display_name":"Analysis of the extra delay on interconnects caused by resistive opens and shorts","publication_year":2009,"publication_date":"2009-06-01","ids":{"openalex":"https://openalex.org/W2084345978","doi":"https://doi.org/10.1109/iolts.2009.5196016","mag":"2084345978"},"language":"en","primary_location":{"id":"doi:10.1109/iolts.2009.5196016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2009.5196016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 15th IEEE International On-Line Testing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060445533","display_name":"Pablo Maqueda","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Pablo Maqueda","raw_affiliation_strings":["Department Enginyeria Electr\u00f2nica, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Dept. Enginyeria Electr\u00f2nica, Universitat Polit\u00e8cnica de Catalunya, Diagonal 647, 9th floor, 08028 Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Department Enginyeria Electr\u00f2nica, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Dept. Enginyeria Electr\u00f2nica, Universitat Polit\u00e8cnica de Catalunya, Diagonal 647, 9th floor, 08028 Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001708745","display_name":"Josep Rius","orcid":"https://orcid.org/0000-0003-2783-6230"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Josep Rius","raw_affiliation_strings":["Department Enginyeria Electr\u00f2nica, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Dept. Enginyeria Electr\u00f2nica, Universitat Polit\u00e8cnica de Catalunya, Diagonal 647, 9th floor, 08028 Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Department Enginyeria Electr\u00f2nica, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Dept. Enginyeria Electr\u00f2nica, Universitat Polit\u00e8cnica de Catalunya, Diagonal 647, 9th floor, 08028 Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5060445533"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":0.53164222,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71872816,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"208","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-touchscreen","display_name":"Resistive touchscreen","score":0.7838337421417236},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6853058338165283},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5700653791427612},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5066495537757874},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.495169073343277},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.4183866083621979},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.35650837421417236},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.3550521731376648},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34204810857772827},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19913867115974426},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1654174029827118}],"concepts":[{"id":"https://openalex.org/C6899612","wikidata":"https://www.wikidata.org/wiki/Q852911","display_name":"Resistive touchscreen","level":2,"score":0.7838337421417236},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6853058338165283},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5700653791427612},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5066495537757874},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.495169073343277},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4183866083621979},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.35650837421417236},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.3550521731376648},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34204810857772827},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19913867115974426},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1654174029827118},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iolts.2009.5196016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iolts.2009.5196016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 15th IEEE International On-Line Testing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1542019159","https://openalex.org/W2108368155","https://openalex.org/W2124692568","https://openalex.org/W2129021480","https://openalex.org/W2165208933","https://openalex.org/W4234831785","https://openalex.org/W6679109355"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W4301193134","https://openalex.org/W3111786897","https://openalex.org/W2020200124","https://openalex.org/W1691923927","https://openalex.org/W2380365775","https://openalex.org/W2109891029","https://openalex.org/W2182628752","https://openalex.org/W2373416410","https://openalex.org/W2101823170"],"abstract_inverted_index":{"The":[0],"paper":[1],"presents":[2],"an":[3,45,61],"analytical":[4],"solution":[5],"for":[6,36,52,73],"the":[7,19,25,37,41,67],"delay":[8],"introduced":[9],"by":[10],"opens":[11],"and":[12,60,64],"shorts":[13],"on":[14],"RC":[15],"interconnects.":[16,77],"Starting":[17],"from":[18,40],"set":[20],"of":[21,27,55,66,75],"PDEs":[22],"that":[23],"defines":[24],"dynamics":[26],"such":[28,76],"lines,":[29],"complete":[30,42],"solutions":[31],"are":[32],"found.":[33],"Compact":[34],"expressions":[35],"delay,":[38],"derived":[39],"solutions,":[43],"show":[44],"excellent":[46],"agreement":[47],"when":[48],"compared":[49],"with":[50],"simulations,":[51],"realistic":[53],"values":[54,63],"interconnect":[56],"parameters,":[57],"driver":[58],"resistance":[59],"arbitrary":[62],"place":[65],"defect.":[68],"This":[69],"information":[70],"is":[71],"useful":[72],"testing":[74]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}