{"id":"https://openalex.org/W2128843244","doi":"https://doi.org/10.1109/intera.2004.1299516","title":"Data movement optimization for software-controlled on-chip memory","display_name":"Data movement optimization for software-controlled on-chip memory","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2128843244","doi":"https://doi.org/10.1109/intera.2004.1299516","mag":"2128843244"},"language":"en","primary_location":{"id":"doi:10.1109/intera.2004.1299516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/intera.2004.1299516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020010462","display_name":"Motonobu Fujita","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Fujita","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","Researcch Center for Adv. Sci. & Technol., Tokyo Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Researcch Center for Adv. Sci. & Technol., Tokyo Univ., Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103017591","display_name":"Masaaki Kondo","orcid":"https://orcid.org/0000-0002-6025-8738"},"institutions":[{"id":"https://openalex.org/I4210086780","display_name":"Japan Science and Technology Agency","ror":"https://ror.org/00097mb19","country_code":"JP","type":"government","lineage":["https://openalex.org/I4210086780"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Kondo","raw_affiliation_strings":["Japan Science and Technology Agency, Kawaguchi, Saitama, Japan","Japan Science and Technology Agency"],"affiliations":[{"raw_affiliation_string":"Japan Science and Technology Agency, Kawaguchi, Saitama, Japan","institution_ids":["https://openalex.org/I4210086780"]},{"raw_affiliation_string":"Japan Science and Technology Agency","institution_ids":["https://openalex.org/I4210086780"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090578339","display_name":"Hiroshi Nakamura","orcid":"https://orcid.org/0009-0005-6505-1903"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Nakamura","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","The University of Tokyo"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Meguro, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"The University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020010462"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.16012006,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"120","last_page":"127"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8202344179153442},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5390452742576599},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5337508916854858},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5225210189819336},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5184369087219238},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48461827635765076},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.484031617641449},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4715321660041809},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44298499822616577},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.410087525844574},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3753231465816498},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3513273596763611},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.25391411781311035},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16468733549118042}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8202344179153442},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5390452742576599},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5337508916854858},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5225210189819336},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5184369087219238},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48461827635765076},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.484031617641449},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4715321660041809},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44298499822616577},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.410087525844574},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3753231465816498},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3513273596763611},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.25391411781311035},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16468733549118042},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/intera.2004.1299516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/intera.2004.1299516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W140465818","https://openalex.org/W1957395430","https://openalex.org/W2016558956","https://openalex.org/W2086134898","https://openalex.org/W2086329118","https://openalex.org/W2092046981","https://openalex.org/W2098220211","https://openalex.org/W2100913437","https://openalex.org/W2116493917","https://openalex.org/W2158158791","https://openalex.org/W2168878642","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W3048967625","https://openalex.org/W2934889147","https://openalex.org/W4248614727","https://openalex.org/W2296275612","https://openalex.org/W1979384060","https://openalex.org/W4379620206","https://openalex.org/W2036525499","https://openalex.org/W4281924108","https://openalex.org/W2043352873","https://openalex.org/W1975698617"],"abstract_inverted_index":{"In":[0,88],"order":[1],"to":[2,31,55],"overcome":[3],"performance":[4,8,58],"degradation":[5],"caused":[6],"by":[7,59,69],"disparity":[9],"between":[10,49],"processor":[11],"and":[12,46,52,123],"main":[13],"memory,":[14],"there":[15],"have":[16,24],"been":[17],"proposed":[18,105,115],"several":[19],"new":[20],"VLSI":[21],"architectures":[22],"which":[23],"software":[25,42],"controlled":[26,43,68],"on-chip":[27,44,51,61,100],"memory":[28,45,120],"in":[29,71],"addition":[30],"the":[32,50,104,114],"conventional":[33,72],"cache.":[34],"However,":[35],"users":[36],"must":[37],"specify":[38],"data":[39,47,94],"allocation/replacement":[40],"on":[41],"transfer":[48],"off-chip":[53],"memories":[54],"achieve":[56,124],"higher":[57],"utilizing":[60],"memory.":[62,101],"Because":[63],"such":[64],"properties":[65],"are":[66],"automatically":[67],"hardware":[70],"caches,":[73],"a":[74,79,82],"cost":[75],"of":[76],"optimization":[77,96],"for":[78,98],"program":[80],"becomes":[81],"matter":[83],"that":[84,113],"should":[85],"be":[86],"considered.":[87],"this":[89],"paper,":[90],"we":[91],"propose":[92],"an":[93],"movement":[95],"technique":[97,116],"software-controlled":[99],"We":[102],"evaluated":[103],"method":[106],"using":[107],"two":[108],"applications.":[109],"The":[110],"results":[111],"reveal":[112],"can":[117],"drastically":[118],"reduce":[119],"stall":[121],"cycles":[122],"high":[125],"performance.":[126]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}