{"id":"https://openalex.org/W2099242001","doi":"https://doi.org/10.1109/intera.2004.1299515","title":"Fast indexing for blocked array layouts to improve multi-level cache locality","display_name":"Fast indexing for blocked array layouts to improve multi-level cache locality","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2099242001","doi":"https://doi.org/10.1109/intera.2004.1299515","mag":"2099242001"},"language":"en","primary_location":{"id":"doi:10.1109/intera.2004.1299515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/intera.2004.1299515","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://doi.org/10.1109/INTERA.2004.1299515","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052482358","display_name":"Evangelia Athanasaki","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"E. Athanasaki","raw_affiliation_strings":["School of Electrical and Computer Engineering, Computing Systems Laboratory, National and Technical University of Athens, Greece","Nat. Tech. Univ. of Athens, Greece"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Computing Systems Laboratory, National and Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Nat. Tech. Univ. of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023526161","display_name":"Nectarios Koziris","orcid":"https://orcid.org/0000-0002-4890-8427"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"N. Koziris","raw_affiliation_strings":["School of Electrical and Computer Engineering, Computing Systems Laboratory, National and Technical University of Athens, Greece","Nat. Tech. Univ. of Athens, Greece"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Computing Systems Laboratory, National and Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Nat. Tech. Univ. of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5052482358"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":1.9111,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.85310379,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"109","last_page":"119"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8570520877838135},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.8106054067611694},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7196888327598572},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.6162943840026855},{"id":"https://openalex.org/keywords/translation-lookaside-buffer","display_name":"Translation lookaside buffer","score":0.5752084255218506},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5592188239097595},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4873881936073303},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.43018895387649536},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.41586410999298096},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.32875436544418335},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25401782989501953},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2473652958869934},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.08742538094520569}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8570520877838135},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.8106054067611694},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7196888327598572},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.6162943840026855},{"id":"https://openalex.org/C116007543","wikidata":"https://www.wikidata.org/wiki/Q1071403","display_name":"Translation lookaside buffer","level":4,"score":0.5752084255218506},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5592188239097595},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4873881936073303},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.43018895387649536},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.41586410999298096},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.32875436544418335},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25401782989501953},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2473652958869934},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.08742538094520569},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/intera.2004.1299515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/intera.2004.1299515","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.","raw_type":"proceedings-article"},{"id":"pmh:oai:dspace.lib.ntua.gr:123456789/31075","is_oa":true,"landing_page_url":"http://doi.org/10.1109/INTERA.2004.1299515","pdf_url":null,"source":{"id":"https://openalex.org/S4377196837","display_name":"DSpace - NTUA (National Technical University of Athens)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I174458059","host_organization_name":"National Technical University of Athens","host_organization_lineage":["https://openalex.org/I174458059"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:dspace.lib.ntua.gr:123456789/31075","is_oa":true,"landing_page_url":"http://doi.org/10.1109/INTERA.2004.1299515","pdf_url":null,"source":{"id":"https://openalex.org/S4377196837","display_name":"DSpace - NTUA (National Technical University of Athens)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I174458059","host_organization_name":"National Technical University of Athens","host_organization_lineage":["https://openalex.org/I174458059"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1515070365","https://openalex.org/W1973122629","https://openalex.org/W2020214444","https://openalex.org/W2038339443","https://openalex.org/W2043958900","https://openalex.org/W2061291998","https://openalex.org/W2069738303","https://openalex.org/W2098220211","https://openalex.org/W2098379190","https://openalex.org/W2100928955","https://openalex.org/W2108315152","https://openalex.org/W2109222446","https://openalex.org/W2119609467","https://openalex.org/W2124727221","https://openalex.org/W2128145051","https://openalex.org/W2132076432","https://openalex.org/W2161823660","https://openalex.org/W2166346826","https://openalex.org/W6630825519","https://openalex.org/W6660195394","https://openalex.org/W6665815944","https://openalex.org/W6674577821","https://openalex.org/W6684519919"],"related_works":["https://openalex.org/W2350803493","https://openalex.org/W1586753310","https://openalex.org/W2121380786","https://openalex.org/W2114591121","https://openalex.org/W2654056874","https://openalex.org/W192356505","https://openalex.org/W4230093848","https://openalex.org/W2951075198","https://openalex.org/W2119502203","https://openalex.org/W2093828978"],"abstract_inverted_index":{"One":[0],"of":[1,56,70,111,135,194,216,222],"the":[2,13,67,97,133,184,190,202,213],"key":[3],"challenges":[4],"computer":[5],"architects":[6],"and":[7,20,168,176],"compiler":[8],"writers":[9],"are":[10,35,74,85,94,127,180],"facing,":[11],"is":[12,45,157,196,210],"increasing":[14],"discrepancy":[15],"between":[16],"processor":[17],"cycle":[18],"times":[19],"main":[21],"memory":[22,42,68,116,223],"access":[23],"times.":[24],"To":[25],"overcome":[26],"this":[27,59],"problem,":[28],"program":[29],"transformations":[30],"that":[31,73,154,206],"decrease":[32],"cache":[33,64,178,217],"misses":[34,179,218],"used,":[36],"to":[37,106,139,212],"reduce":[38,63],"average":[39],"latency":[40],"for":[41,53,123,183],"accesses.":[43],"Tiling":[44],"a":[46,88,103],"widely":[47],"used":[48],"loop":[49],"iteration":[50],"reordering":[51],"technique":[52],"improving":[54],"locality":[55,193],"references.":[57],"In":[58,80],"paper,":[60],"we":[61],"further":[62],"misses,":[65],"restructuring":[66],"layout":[69,117],"multi-dimensional":[71,109],"arrays,":[72],"accessed":[75],"by":[76,96],"tiled":[77,98,162,165],"instruction":[78,99],"code.":[79],"our":[81,207],"method,":[82],"array":[83,125,166],"elements":[84],"stored":[86],"in":[87,219],"blocked":[89,115],"way,":[90],"exactly":[91],"as":[92],"they":[93],"swept":[95],"stream.":[100],"We":[101],"present":[102],"straightforward":[104],"way":[105],"easily":[107,129],"translate":[108],"indexing":[110],"arrays":[112],"into":[113],"their":[114],"using":[118,150,201],"simple":[119],"binary-mask":[120],"operations.":[121],"Indices":[122],"such":[124],"layouts":[126,167],"now":[128],"calculated":[130],"based":[131],"on":[132,145],"algebra":[134],"dilated":[136],"integers,":[137],"similarly":[138],"morton-order":[140],"indexing.":[141],"Actual":[142],"experimental":[143],"results":[144],"three":[146],"different":[147],"hardware":[148],"platforms,":[149],"5":[151],"benchmarks,":[152],"illustrate":[153],"execution":[155],"time":[156],"greatly":[158,197],"improved":[159],"when":[160],"combining":[161],"code":[163],"with":[164],"binary":[169],"mask-based":[170],"index":[171],"translation":[172],"functions.":[173],"Both":[174],"TLB":[175],"L1":[177],"concurrently":[181],"minimized,":[182],"same":[185],"tile":[186],"size,":[187],"thus,":[188],"applying":[189],"proposed":[191],"layouts,":[192],"references":[195],"improved.":[198],"Finally,":[199],"simulations":[200],"Simplescalar":[203],"tool,":[204],"verify":[205],"enhanced":[208],"performance":[209],"due":[211],"considerable":[214],"reduction":[215],"all":[220],"levels":[221],"hierarchy.":[224]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}