{"id":"https://openalex.org/W4398775014","doi":"https://doi.org/10.1109/imw59701.2024.10536951","title":"Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory","display_name":"Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory","publication_year":2024,"publication_date":"2024-05-12","ids":{"openalex":"https://openalex.org/W4398775014","doi":"https://doi.org/10.1109/imw59701.2024.10536951"},"language":"en","primary_location":{"id":"doi:10.1109/imw59701.2024.10536951","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/imw59701.2024.10536951","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Memory Workshop (IMW)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067147831","display_name":"Noboru Shibata","orcid":"https://orcid.org/0000-0002-1988-2520"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Noboru Shibata","raw_affiliation_strings":["Kioxia Corporation,Institute of Memory Technology Research &#x0026; Development,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kioxia Corporation,Institute of Memory Technology Research &#x0026; Development,Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085619623","display_name":"Hironori Uchikawa","orcid":"https://orcid.org/0000-0001-7517-445X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hironori Uchikawa","raw_affiliation_strings":["Kioxia Corporation,Institute of Memory Technology Research &#x0026; Development,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kioxia Corporation,Institute of Memory Technology Research &#x0026; Development,Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112582829","display_name":"Taira Shibuya","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Taira Shibuya","raw_affiliation_strings":["Kioxia Corporation,Memory Div.,Japan","Memory Div., Kioxia Corporation, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kioxia Corporation,Memory Div.,Japan","institution_ids":[]},{"raw_affiliation_string":"Memory Div., Kioxia Corporation, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108492826","display_name":"Hirofumi Inoue","orcid":"https://orcid.org/0009-0001-4413-5746"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hirofumi Inoue","raw_affiliation_strings":["Kioxia Corporation,Memory Development Strategy Div.,Japan","Memory Development Strategy Div., Kioxia Corporation, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kioxia Corporation,Memory Development Strategy Div.,Japan","institution_ids":[]},{"raw_affiliation_string":"Memory Development Strategy Div., Kioxia Corporation, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5061,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.78962076,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9865999817848206,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9865999817848206,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9684000015258789,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9674999713897705,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8045254945755005},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.6140218377113342},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5907842516899109},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5259499549865723},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5250927209854126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4632583260536194},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.42400527000427246},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4194273352622986},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3238462209701538},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2712373733520508},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21313315629959106}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8045254945755005},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.6140218377113342},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5907842516899109},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5259499549865723},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5250927209854126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4632583260536194},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.42400527000427246},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4194273352622986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3238462209701538},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2712373733520508},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21313315629959106},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/imw59701.2024.10536951","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/imw59701.2024.10536951","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Memory Workshop (IMW)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2331884666","https://openalex.org/W3015201175","https://openalex.org/W4380302634","https://openalex.org/W4385192446","https://openalex.org/W6634039917"],"related_works":["https://openalex.org/W4236038575","https://openalex.org/W2375427054","https://openalex.org/W4390045048","https://openalex.org/W1619771466","https://openalex.org/W4230076341","https://openalex.org/W2172040660","https://openalex.org/W2269245812","https://openalex.org/W1554452560","https://openalex.org/W1983262605","https://openalex.org/W3207862145"],"abstract_inverted_index":{"This":[0,46],"study":[1],"introduces":[2],"a":[3,21],"novel":[4],"multi-level":[5,16,27,44],"coding":[6],"and":[7,25,70],"architecture":[8],"designed":[9],"to":[10],"enhance":[11],"random":[12,63,73],"access":[13,64,74],"time":[14,65],"in":[15,59,75],"flash":[17],"memory.":[18],"By":[19],"employing":[20],"strategy":[22],"of":[23,37,68],"sharing":[24],"storing":[26],"data":[28],"across":[29],"multiple":[30],"memory":[31],"cells,":[32],"we":[33],"address":[34],"the":[35],"challenge":[36],"increased":[38],"read":[39],"cycles":[40],"typically":[41],"associated":[42],"with":[43,66],"data.":[45],"architecture,":[47],"which":[48],"does":[49],"not":[50],"require":[51],"new":[52],"processes":[53],"or":[54],"materials,":[55],"achieves":[56],"one-cycle":[57],"reading":[58],"MLC,":[60],"equating":[61],"its":[62],"that":[67],"SLC,":[69],"ensures":[71],"rapid":[72],"TLC.":[76]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-08-27T14:10:00.468798","created_date":"2025-10-10T00:00:00"}
