{"id":"https://openalex.org/W4380302680","doi":"https://doi.org/10.1109/imw56887.2023.10145823","title":"A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device","display_name":"A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device","publication_year":2023,"publication_date":"2023-05-01","ids":{"openalex":"https://openalex.org/W4380302680","doi":"https://doi.org/10.1109/imw56887.2023.10145823"},"language":"en","primary_location":{"id":"doi:10.1109/imw56887.2023.10145823","is_oa":false,"landing_page_url":"https://doi.org/10.1109/imw56887.2023.10145823","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Memory Workshop (IMW)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081562363","display_name":"Wei-Chen Chen","orcid":"https://orcid.org/0000-0002-3711-818X"},"institutions":[{"id":"https://openalex.org/I4210092191","display_name":"Macronix International (Taiwan)","ror":"https://ror.org/01bggjn73","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210092191"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Wei-Chen Chen","raw_affiliation_strings":["Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I4210092191"]},{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210092191"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089084441","display_name":"Hang-Ting Lue","orcid":"https://orcid.org/0000-0003-1078-1333"},"institutions":[{"id":"https://openalex.org/I4210092191","display_name":"Macronix International (Taiwan)","ror":"https://ror.org/01bggjn73","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210092191"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hang-Ting Lue","raw_affiliation_strings":["Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I4210092191"]},{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210092191"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102736718","display_name":"Tzu\u2010Hsuan Hsu","orcid":"https://orcid.org/0000-0001-5776-7489"},"institutions":[{"id":"https://openalex.org/I4210092191","display_name":"Macronix International (Taiwan)","ror":"https://ror.org/01bggjn73","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210092191"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tzu-Hsuan Hsu","raw_affiliation_strings":["Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I4210092191"]},{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210092191"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028102750","display_name":"Keh-Chung Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092191","display_name":"Macronix International (Taiwan)","ror":"https://ror.org/01bggjn73","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210092191"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Keh-Chung Wang","raw_affiliation_strings":["Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I4210092191"]},{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210092191"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024808324","display_name":"Chih-Yuan Lu","orcid":"https://orcid.org/0000-0002-8951-2509"},"institutions":[{"id":"https://openalex.org/I4210092191","display_name":"Macronix International (Taiwan)","ror":"https://ror.org/01bggjn73","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210092191"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Yuan Lu","raw_affiliation_strings":["Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I4210092191"]},{"raw_affiliation_string":"Macronix International Co., Ltd 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210092191"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5081562363"],"corresponding_institution_ids":["https://openalex.org/I4210092191"],"apc_list":null,"apc_paid":null,"fwci":0.9142,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.73722119,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9429581165313721},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5736308097839355},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5508723258972168},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5117725729942322},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5099657773971558},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.5073608756065369},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4925897717475891},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.46894311904907227},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.44571730494499207},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4326876401901245},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3285568058490753},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2869337201118469},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21280449628829956},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16747382283210754},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.08852913975715637}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9429581165313721},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5736308097839355},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5508723258972168},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5117725729942322},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5099657773971558},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.5073608756065369},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4925897717475891},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.46894311904907227},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.44571730494499207},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4326876401901245},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3285568058490753},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2869337201118469},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21280449628829956},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16747382283210754},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.08852913975715637},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/imw56887.2023.10145823","is_oa":false,"landing_page_url":"https://doi.org/10.1109/imw56887.2023.10145823","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Memory Workshop (IMW)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W3003352156"],"related_works":["https://openalex.org/W2140607147","https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W1976244802","https://openalex.org/W2083934844","https://openalex.org/W1992487929"],"abstract_inverted_index":{"Planar":[0],"1T1C":[1,62,75],"DRAM":[2,63,207],"has":[3],"encountered":[4],"numerous":[5],"challenges":[6],"as":[7],"it":[8],"reaches":[9],"beyond":[10],"$1":[11],"\\mathrm{z}-\\mathrm{nm}$":[12],"node.":[13],"The":[14,158],"daunting":[15],"task":[16],"of":[17,41,70,99,108,122,180],"manufacturing":[18],"a":[19,28,110,193],"low-leakage":[20],"access":[21],"transistor":[22],"and":[23,64,80,102,135,185],"high":[24],"aspectratio":[25],"capacitor":[26],"necessitates":[27],"disruptive":[29],"technology":[30],"to":[31,38,44],"continue":[32],"the":[33,39,56,67,90,96,116,132,141,149,156,203],"relentless":[34],"scaling":[35,57,117,201],"path":[36],"similar":[37],"migration":[40],"$2":[42],"D$":[43,46,205],"$3":[45,204],"NAND.":[47],"In":[48],"this":[49],"work,":[50],"we":[51],"will":[52,87],"touch":[53],"up":[54],"on":[55],"difficulties":[58],"associated":[59],"with":[60],"2D":[61],"then":[65],"examine":[66],"possible":[68],"options":[69],"3D":[71,81,103,112],"DRAM,":[72,76,79,93],"including":[73],"flipped":[74],"2T0C":[77],"gain-cell":[78],"stackable":[82,113,206],"gate-controlled-thyristor":[83],"(GCT)":[84],"DRAM.":[85],"We":[86],"show":[88],"that":[89],"capacitor-less":[91],"GCT":[92,124,164],"which":[94],"shares":[95],"architectural":[97],"features":[98],"CMOS":[100],"nanosheet":[101],"NAND,":[104],"possesses":[105],"good":[106],"potential":[107],"realizing":[109],"truly":[111],"structure.":[114],"Furthermore,":[115],"capability":[118],"toward":[119],"$10":[120],"\\mathrm{~nm}$":[121,163],"such":[123],"device":[125,165],"is":[126,146],"verified":[127],"by":[128],"TCAD":[129],"simulation":[130],"when":[131],"channel":[133],"length":[134],"width":[136],"are":[137,153],"downscaled":[138],"simultaneously.":[139],"Meanwhile,":[140],"gate":[142],"oxide":[143],"thickness":[144],"thinning":[145],"unnecessary":[147],"because":[148],"thyristor":[150],"operation":[151],"principles":[152],"different":[154],"from":[155],"MOSFET.":[157],"simulated":[159],"$\\mathrm{Lch}":[160],"/":[161,198],"\\mathrm{Wch}=10":[162],"can":[166],"well":[167],"preserve":[168],"$\\gt":[169,181],"2":[170],"\\mathrm{~V}$":[171],"hysteresis":[172],"memory":[173],"window,":[174,191],"large":[175],"read":[176],"current":[177,190],"ON/OFF":[178],"ratio":[179],"1":[182],"E":[183],"8$,":[184],"$110":[186],"\\mu":[187],"\\mathrm{A}$":[188],"sensing":[189],"paving":[192],"way":[194],"for":[195,202],"aggressive":[196],"$X":[197],"Y$":[199],"pitch":[200],"device.":[208]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-27T14:29:43.386196","created_date":"2025-10-10T00:00:00"}
