{"id":"https://openalex.org/W2897559245","doi":"https://doi.org/10.1109/ijcnn.2018.8489263","title":"Digital Realization of PSTDP and TSTDP Learning","display_name":"Digital Realization of PSTDP and TSTDP Learning","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2897559245","doi":"https://doi.org/10.1109/ijcnn.2018.8489263","mag":"2897559245"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2018.8489263","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2018.8489263","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Joint Conference on Neural Networks (IJCNN)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026827696","display_name":"Shaghayegh Gomar","orcid":"https://orcid.org/0000-0001-9298-4358"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Shaghayegh Gomar","raw_affiliation_strings":["Research Centre for Integrated Microsystems, Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Research Centre for Integrated Microsystems, Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035412745","display_name":"Majid Ahmadi","orcid":"https://orcid.org/0000-0001-5781-6754"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Majid Ahmadi","raw_affiliation_strings":["Research Centre for Integrated Microsystems, Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Research Centre for Integrated Microsystems, Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5026827696"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.7725,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.74246447,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12611","display_name":"Neural Networks and Reservoir Computing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8804507255554199},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7836937308311462},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7623497247695923},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6432273387908936},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6216216683387756},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5827004313468933},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4366293251514435},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.41952836513519287},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.41722768545150757},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.40431106090545654},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35202208161354065},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3117026090621948},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30964577198028564},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.28395354747772217},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1300814151763916},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10248586535453796},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0726182758808136}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8804507255554199},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7836937308311462},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7623497247695923},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6432273387908936},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6216216683387756},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5827004313468933},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4366293251514435},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.41952836513519287},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.41722768545150757},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40431106090545654},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35202208161354065},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3117026090621948},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30964577198028564},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.28395354747772217},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1300814151763916},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10248586535453796},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0726182758808136},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ijcnn.2018.8489263","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2018.8489263","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Joint Conference on Neural Networks (IJCNN)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1975412204","https://openalex.org/W2037748403","https://openalex.org/W2038540384","https://openalex.org/W2045917633","https://openalex.org/W2054455878","https://openalex.org/W2128589492","https://openalex.org/W2167425979","https://openalex.org/W2544134426","https://openalex.org/W3104751959"],"related_works":["https://openalex.org/W2155289750","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W2914607376","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W3026940965","https://openalex.org/W2803475965","https://openalex.org/W2164587072"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"low":[3],"cost,":[4],"accurate":[5],"and":[6,12,17,35,42,56,66,105],"configurable":[7],"digital":[8,54],"circuits":[9,55,62,79,88],"for":[10],"pair-based":[11],"triplet-based":[13],"STDP":[14],"learning":[15,59],"models,":[16],"the":[18,24,27,52,57,77,84],"proposed":[19,53,78],"architectures":[20],"are":[21],"compared":[22],"with":[23],"state":[25],"of":[26,49,83],"art":[28],"approaches":[29],"such":[30],"as":[31],"Lookup":[32],"table":[33],"(LUT),":[34],"Piecewise":[36],"Linear":[37],"approximation":[38],"(PWL).":[39],"Experimental":[40],"results":[41,74],"error":[43,48],"measurements":[44],"indicate":[45],"a":[46,93],"maximum":[47,81],"0.0088":[50],"between":[51],"original":[58],"models.":[60],"The":[61,87],"have":[63],"been":[64],"synthesized":[65],"physically":[67],"implemented":[68],"on":[69],"Altera":[70],"FPGA":[71,85],"board.":[72],"Synthesis":[73],"verify":[75],"that":[76],"take":[80],"1%":[82],"resources.":[86],"can":[89],"be":[90],"employed":[91],"in":[92],"large":[94],"scale":[95],"Spiking":[96],"Neural":[97],"Network":[98],"(SNN)":[99],"implementation":[100],"due":[101],"to":[102],"their":[103],"compactness":[104],"configurability.":[106]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}