{"id":"https://openalex.org/W2157684086","doi":"https://doi.org/10.1109/ijcnn.2004.1381174","title":"Trends in design of massively parallel coprocessors implemented in digital ASICs","display_name":"Trends in design of massively parallel coprocessors implemented in digital ASICs","publication_year":2005,"publication_date":"2005-02-28","ids":{"openalex":"https://openalex.org/W2157684086","doi":"https://doi.org/10.1109/ijcnn.2004.1381174","mag":"2157684086"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2004.1381174","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2004.1381174","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058936770","display_name":"P\u00e9ter F\u00f6ldesy","orcid":"https://orcid.org/0000-0002-5974-064X"},"institutions":[{"id":"https://openalex.org/I7597260","display_name":"Hungarian Academy of Sciences","ror":"https://ror.org/02ks8qq67","country_code":"HU","type":"funder","lineage":["https://openalex.org/I7597260"]},{"id":"https://openalex.org/I198412221","display_name":"HUN-REN Institute for Nuclear Research","ror":"https://ror.org/006vxbq87","country_code":"HU","type":"facility","lineage":["https://openalex.org/I198412221","https://openalex.org/I4387152226"]},{"id":"https://openalex.org/I4210117195","display_name":"Institute for Computer Science and Control","ror":"https://ror.org/0249v7n71","country_code":"HU","type":"facility","lineage":["https://openalex.org/I4210117195","https://openalex.org/I7597260"]}],"countries":["HU"],"is_corresponding":true,"raw_author_name":"P. Foldesy","raw_affiliation_strings":["Analogic and Neural Computing Laboratory Computer and Automation Research Institute, Hungarian Academy of Sciences (ATOMKI), Budapest, Hungary"],"affiliations":[{"raw_affiliation_string":"Analogic and Neural Computing Laboratory Computer and Automation Research Institute, Hungarian Academy of Sciences (ATOMKI), Budapest, Hungary","institution_ids":["https://openalex.org/I7597260","https://openalex.org/I198412221","https://openalex.org/I4210117195"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5058936770"],"corresponding_institution_ids":["https://openalex.org/I198412221","https://openalex.org/I4210117195","https://openalex.org/I7597260"],"apc_list":null,"apc_paid":null,"fwci":0.8207,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79977936,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"3131","last_page":"3135"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.9036509394645691},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.8692182302474976},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7473300695419312},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5500282049179077},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5456538796424866},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5236392021179199},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48125120997428894},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.47199538350105286},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.43602675199508667},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.4246925115585327},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.42429643869400024},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.413104385137558},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3224182724952698},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10354563593864441}],"concepts":[{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.9036509394645691},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.8692182302474976},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7473300695419312},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5500282049179077},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5456538796424866},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5236392021179199},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48125120997428894},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.47199538350105286},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.43602675199508667},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.4246925115585327},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.42429643869400024},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.413104385137558},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3224182724952698},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10354563593864441},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ijcnn.2004.1381174","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2004.1381174","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)","raw_type":"proceedings-article"},{"id":"pmh:oai:eprints.sztaki.hu:3735","is_oa":false,"landing_page_url":"http://eprints.sztaki.hu/3735/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401907","display_name":"SZTAKI Publication Repository (Hungarian Academy of Sciences)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I7597260","host_organization_name":"Hungarian Academy of Sciences","host_organization_lineage":["https://openalex.org/I7597260"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference or Workshop Item"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1514201420","https://openalex.org/W1530132974","https://openalex.org/W1562910257","https://openalex.org/W1827834298","https://openalex.org/W1887556625","https://openalex.org/W1978100713","https://openalex.org/W2018630400","https://openalex.org/W2070314832","https://openalex.org/W2098284001","https://openalex.org/W2104078694","https://openalex.org/W2117099910","https://openalex.org/W2122283876","https://openalex.org/W2137570657","https://openalex.org/W2146665136","https://openalex.org/W2147071988","https://openalex.org/W2159448186","https://openalex.org/W2159741920","https://openalex.org/W2172212694","https://openalex.org/W2173674295","https://openalex.org/W4234479839","https://openalex.org/W6630657665","https://openalex.org/W6633663999","https://openalex.org/W6639711652","https://openalex.org/W6683184667"],"related_works":["https://openalex.org/W2157684086","https://openalex.org/W2609406488","https://openalex.org/W2172228568","https://openalex.org/W1943306263","https://openalex.org/W2136856495","https://openalex.org/W2102735377","https://openalex.org/W2154741861","https://openalex.org/W2090758225","https://openalex.org/W1998817374","https://openalex.org/W2969260674"],"abstract_inverted_index":{"This":[0],"paper":[1],"collects":[2],"the":[3,10,17,28,32,40,53,57,66],"most":[4],"recent":[5,11,54],"parallel":[6,21],"coprocessors":[7],"and":[8,61,65],"highlights":[9],"trends.":[12],"It":[13],"is":[14,56],"shown":[15],"that":[16],"single":[18],"chip":[19],"massively":[20],"processor":[22],"implementations":[23],"seem":[24],"to":[25,72],"disappear":[26],"from":[27],"scientific":[29],"investigations":[30],"(with":[31],"exception":[33],"of":[34,52],"low-level":[35],"near-sensor":[36],"image":[37],"processing).":[38],"Meanwhile,":[39],"formerly":[41],"developed":[42],"architectures":[43,55],"have":[44],"moved":[45],"inside":[46],"complex":[47],"system-on-chips/microprocessors.":[48],"The":[49],"common":[50],"aspect":[51],"advanced":[58],"processing":[59,75],"element":[60,76],"internal":[62],"interconnection":[63],"solutions,":[64],"dominant":[67],"mid-grain":[68],"parallelism":[69],"(i.e.":[70],"up":[71],"a":[73],"hundred":[74],"per":[77],"chip).":[78]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
