{"id":"https://openalex.org/W2141468038","doi":"https://doi.org/10.1109/ijcnn.2004.1381063","title":"RTD-based compact programmable gates","display_name":"RTD-based compact programmable gates","publication_year":2005,"publication_date":"2005-02-28","ids":{"openalex":"https://openalex.org/W2141468038","doi":"https://doi.org/10.1109/ijcnn.2004.1381063","mag":"2141468038"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2004.1381063","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2004.1381063","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114376210","display_name":"J.M. Quintana","orcid":"https://orcid.org/0000-0003-1479-0050"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210147934","display_name":"Centro Nacional de Microelectr\u00f3nica","ror":"https://ror.org/03ycqrz18","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210147934"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J.M. Quintana","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, Centra Nacional de Microelectr\u00f3nica, Seville, Spain","Centre Nacional de Microelectronica, Institute de Microelectronica de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, Centra Nacional de Microelectr\u00f3nica, Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Centre Nacional de Microelectronica, Institute de Microelectronica de Sevilla, Spain","institution_ids":["https://openalex.org/I4210147934"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031060766","display_name":"M.J. Avedillo","orcid":"https://orcid.org/0000-0002-8345-8441"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210147934","display_name":"Centro Nacional de Microelectr\u00f3nica","ror":"https://ror.org/03ycqrz18","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210147934"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"M.J. Avedillo","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, Centra Nacional de Microelectr\u00f3nica, Seville, Spain","Centre Nacional de Microelectronica, Institute de Microelectronica de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, Centra Nacional de Microelectr\u00f3nica, Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Centre Nacional de Microelectronica, Institute de Microelectronica de Sevilla, Spain","institution_ids":["https://openalex.org/I4210147934"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110073108","display_name":"H\u00e9ctor Pettenghi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210147934","display_name":"Centro Nacional de Microelectr\u00f3nica","ror":"https://ror.org/03ycqrz18","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210147934"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"H. Pettenghi","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, Centra Nacional de Microelectr\u00f3nica, Seville, Spain","Centre Nacional de Microelectronica, Institute de Microelectronica de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, Centra Nacional de Microelectr\u00f3nica, Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Centre Nacional de Microelectronica, Institute de Microelectronica de Sevilla, Spain","institution_ids":["https://openalex.org/I4210147934"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3634,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.68252435,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"4","issue":null,"first_page":"2637","last_page":"2640"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10022","display_name":"Semiconductor Quantum Structures and Devices","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5987498760223389},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.53862464427948},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.536566436290741},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5256819725036621},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5250106453895569},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5064152479171753},{"id":"https://openalex.org/keywords/diode","display_name":"Diode","score":0.4567093253135681},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42607855796813965},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.40437835454940796},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3211875557899475},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21422067284584045},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20397576689720154}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5987498760223389},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.53862464427948},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.536566436290741},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5256819725036621},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5250106453895569},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5064152479171753},{"id":"https://openalex.org/C78434282","wikidata":"https://www.wikidata.org/wiki/Q11656","display_name":"Diode","level":2,"score":0.4567093253135681},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42607855796813965},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.40437835454940796},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3211875557899475},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21422067284584045},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20397576689720154}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ijcnn.2004.1381063","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2004.1381063","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1537198282","https://openalex.org/W1590442818","https://openalex.org/W1968351651","https://openalex.org/W2017624429","https://openalex.org/W2108860940","https://openalex.org/W2128725931","https://openalex.org/W2140332259","https://openalex.org/W2148972210"],"related_works":["https://openalex.org/W3117015220","https://openalex.org/W3013792460","https://openalex.org/W1904803855","https://openalex.org/W1528933814","https://openalex.org/W2170504327","https://openalex.org/W2526300902","https://openalex.org/W2765224956","https://openalex.org/W2160055326","https://openalex.org/W1968351651","https://openalex.org/W1681536465"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"novel":[3],"and":[4,28,34,55,72],"extremely":[5],"compact":[6],"implementations":[7],"of":[8,14,23,44,67],"programmable":[9,61,68],"gates":[10,62,69],"on":[11,40],"the":[12,15,41,56],"basis":[13],"multi-threshold":[16],"threshold":[17],"gate":[18],"concept.":[19],"The":[20,48],"circuit":[21,51],"consists":[22],"resonant":[24],"tunnelling":[25],"diodes":[26],"(RTDs)":[27],"heterostructure":[29],"field":[30],"effect":[31],"transistors":[32],"(HFETs)":[33],"its":[35],"operating":[36],"principle":[37],"is":[38,53,63,75],"based":[39],"controlled":[42],"quenching":[43],"clocked":[45],"series-connected":[46],"RTDs.":[47],"proposed":[49],"generic":[50],"topology":[52],"presented":[54],"methodology":[57],"to":[58],"design":[59],"specific":[60],"introduced.":[64],"A":[65],"number":[66],"are":[70],"shown":[71],"their":[73],"operation":[74],"validated.":[76]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}