{"id":"https://openalex.org/W2144100916","doi":"https://doi.org/10.1109/ijcnn.2004.1379971","title":"Mapping LSSVM on digital hardware","display_name":"Mapping LSSVM on digital hardware","publication_year":2005,"publication_date":"2005-02-22","ids":{"openalex":"https://openalex.org/W2144100916","doi":"https://doi.org/10.1109/ijcnn.2004.1379971","mag":"2144100916"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2004.1379971","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2004.1379971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036611143","display_name":"Davide Anguita","orcid":"https://orcid.org/0000-0001-7523-5291"},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"D. Anguita","raw_affiliation_strings":["DIBE-Department of Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy","Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy"],"affiliations":[{"raw_affiliation_string":"DIBE-Department of Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]},{"raw_affiliation_string":"Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032000935","display_name":"Andrea Boni","orcid":"https://orcid.org/0000-0001-7649-2871"},"institutions":[{"id":"https://openalex.org/I193223587","display_name":"University of Trento","ror":"https://ror.org/05trd4x28","country_code":"IT","type":"education","lineage":["https://openalex.org/I193223587"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Boni","raw_affiliation_strings":["DIT-Department of Information and Communication Technology, University of Trento, Trento, Italy","University of Trento"],"affiliations":[{"raw_affiliation_string":"DIT-Department of Information and Communication Technology, University of Trento, Trento, Italy","institution_ids":["https://openalex.org/I193223587"]},{"raw_affiliation_string":"University of Trento","institution_ids":["https://openalex.org/I193223587"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032151322","display_name":"Alessandro Zorat","orcid":null},"institutions":[{"id":"https://openalex.org/I193223587","display_name":"University of Trento","ror":"https://ror.org/05trd4x28","country_code":"IT","type":"education","lineage":["https://openalex.org/I193223587"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Zorat","raw_affiliation_strings":["DIT-Department of Information and Communication Technology, University of Trento, Trento, Italy","University of Trento"],"affiliations":[{"raw_affiliation_string":"DIT-Department of Information and Communication Technology, University of Trento, Trento, Italy","institution_ids":["https://openalex.org/I193223587"]},{"raw_affiliation_string":"University of Trento","institution_ids":["https://openalex.org/I193223587"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5036611143"],"corresponding_institution_ids":["https://openalex.org/I83816512"],"apc_list":null,"apc_paid":null,"fwci":0.3367,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.64664939,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"567","last_page":"571"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8559390306472778},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7531758546829224},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.7029985785484314},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.601012110710144},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5795591473579407},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5018985271453857},{"id":"https://openalex.org/keywords/vector-quantization","display_name":"Vector quantization","score":0.4371558129787445},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3418004512786865},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3367731273174286},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21700707077980042},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14806151390075684},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09439727663993835}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8559390306472778},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7531758546829224},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.7029985785484314},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.601012110710144},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5795591473579407},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5018985271453857},{"id":"https://openalex.org/C199833920","wikidata":"https://www.wikidata.org/wiki/Q612536","display_name":"Vector quantization","level":2,"score":0.4371558129787445},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3418004512786865},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3367731273174286},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21700707077980042},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14806151390075684},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09439727663993835},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/ijcnn.2004.1379971","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2004.1379971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.127.6803","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.127.6803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.smartlab.dibe.unige.it/files/publication/pdf/c039.pdf","raw_type":"text"},{"id":"pmh:oai:iris.unige.it:11567/315666","is_oa":false,"landing_page_url":"http://hdl.handle.net/11567/315666","pdf_url":null,"source":{"id":"https://openalex.org/S4377196291","display_name":"CINECA IRIS Institutial Research Information System (University of Genoa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I83816512","host_organization_name":"University of Genoa","host_organization_lineage":["https://openalex.org/I83816512"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:iris.unitn.it:11572/50468","is_oa":false,"landing_page_url":"http://hdl.handle.net/11572/50468","pdf_url":null,"source":{"id":"https://openalex.org/S4306401913","display_name":"Institutional Research Information System (Universit\u00e0 degli Studi di Trento)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I193223587","host_organization_name":"University of Trento","host_organization_lineage":["https://openalex.org/I193223587"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1501773990","https://openalex.org/W1550041041","https://openalex.org/W1596717185","https://openalex.org/W2031601132","https://openalex.org/W2040593995","https://openalex.org/W2060924166","https://openalex.org/W2101816156","https://openalex.org/W2102696274","https://openalex.org/W2104226279","https://openalex.org/W2107383972","https://openalex.org/W2148510975","https://openalex.org/W2148603752","https://openalex.org/W2151388232","https://openalex.org/W2169828376","https://openalex.org/W3023786531"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W3209251257","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2281932057","https://openalex.org/W2015815070","https://openalex.org/W2127430515","https://openalex.org/W1966261340"],"abstract_inverted_index":{"In":[0,13],"this":[1],"paper":[2],"we":[3,15,47],"show":[4],"how":[5],"to":[6,24,30],"map":[7],"a":[8,17,42,49,61],"LSSVM":[9],"on":[10],"digital":[11],"hardware.":[12],"particular,":[14],"provide":[16],"theoretical":[18],"analysis":[19],"of":[20,39,60],"quantization":[21],"effects,":[22],"due":[23],"finite":[25],"register":[26],"lengths,":[27],"that":[28],"leads":[29],"some":[31],"useful":[32],"bounds":[33],"for":[34,41],"computing":[35],"the":[36,53,57],"necessary":[37],"number":[38],"bits":[40],"correct":[43],"hardware":[44],"implementation.":[45],"Then,":[46],"describe":[48],"new":[50],"FPGA-based":[51],"architecture,":[52],"KTRON,":[54],"which":[55],"implements":[56],"feed-forward":[58],"phase":[59],"LSSVM.":[62]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
