{"id":"https://openalex.org/W1822151324","doi":"https://doi.org/10.1109/ijcnn.2003.1223849","title":"Piecewise-linear modeling of analog circuits using trained feed-forward neural networks and adaptive clustering of hidden neurons","display_name":"Piecewise-linear modeling of analog circuits using trained feed-forward neural networks and adaptive clustering of hidden neurons","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W1822151324","doi":"https://doi.org/10.1109/ijcnn.2003.1223849","mag":"1822151324"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2003.1223849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2003.1223849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Joint Conference on Neural Networks, 2003.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005741308","display_name":"Simona Doboli","orcid":"https://orcid.org/0000-0003-0158-4725"},"institutions":[{"id":"https://openalex.org/I139290212","display_name":"Hofstra University","ror":"https://ror.org/03pm18j10","country_code":"US","type":"education","lineage":["https://openalex.org/I139290212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Doboli","raw_affiliation_strings":["Computer Science Department, Hofstra University, Hempstead, NY, USA","Dept. of Comput. Sci., Hofstra Univ., Hempstead, NY, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, Hofstra University, Hempstead, NY, USA","institution_ids":["https://openalex.org/I139290212"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Hofstra Univ., Hempstead, NY, USA#TAB#","institution_ids":["https://openalex.org/I139290212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083259503","display_name":"G. Gothoskar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087560","display_name":"Stony Brook School","ror":"https://ror.org/003wx9n05","country_code":"US","type":"education","lineage":["https://openalex.org/I4210087560"]},{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Gothoskar","raw_affiliation_strings":["VLSI Systems Design Laboratory, Electrical and Computer Engineering Department, SUNY Stony Brook, Stony Brook, NY, USA","Stony Brook University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Systems Design Laboratory, Electrical and Computer Engineering Department, SUNY Stony Brook, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I4210087560","https://openalex.org/I59553526"]},{"raw_affiliation_string":"Stony Brook University","institution_ids":["https://openalex.org/I59553526"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080972445","display_name":"Alex Doboli","orcid":"https://orcid.org/0000-0003-2472-4014"},"institutions":[{"id":"https://openalex.org/I4210087560","display_name":"Stony Brook School","ror":"https://ror.org/003wx9n05","country_code":"US","type":"education","lineage":["https://openalex.org/I4210087560"]},{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Doboli","raw_affiliation_strings":["VLSI Systems Design Laboratory, Electrical and Computer Engineering Department, SUNY Stony Brook, Stony Brook, NY, USA","Stony Brook University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Systems Design Laboratory, Electrical and Computer Engineering Department, SUNY Stony Brook, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I4210087560","https://openalex.org/I59553526"]},{"raw_affiliation_string":"Stony Brook University","institution_ids":["https://openalex.org/I59553526"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.6547,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.81965577,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"1126","last_page":"1131"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.702104926109314},{"id":"https://openalex.org/keywords/piecewise-linear-function","display_name":"Piecewise linear function","score":0.613900899887085},{"id":"https://openalex.org/keywords/linear-circuit","display_name":"Linear circuit","score":0.5777878165245056},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5603703260421753},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.5181192755699158},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4816921651363373},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4721146821975708},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4533793032169342},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.44580143690109253},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.41807451844215393},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.41636785864830017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3765096366405487},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.36013954877853394},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.3507816195487976},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.30410122871398926},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.21177032589912415},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17750519514083862},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1374691128730774}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.702104926109314},{"id":"https://openalex.org/C17095337","wikidata":"https://www.wikidata.org/wiki/Q2375229","display_name":"Piecewise linear function","level":2,"score":0.613900899887085},{"id":"https://openalex.org/C194571574","wikidata":"https://www.wikidata.org/wiki/Q2251187","display_name":"Linear circuit","level":4,"score":0.5777878165245056},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5603703260421753},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.5181192755699158},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4816921651363373},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4721146821975708},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4533793032169342},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.44580143690109253},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.41807451844215393},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.41636785864830017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3765096366405487},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.36013954877853394},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.3507816195487976},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.30410122871398926},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.21177032589912415},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17750519514083862},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1374691128730774},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ijcnn.2003.1223849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2003.1223849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Joint Conference on Neural Networks, 2003.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1504265359","https://openalex.org/W1530621902","https://openalex.org/W1547466200","https://openalex.org/W1581032717","https://openalex.org/W1584092455","https://openalex.org/W1986873938","https://openalex.org/W2006594212","https://openalex.org/W2054804336","https://openalex.org/W2085399494","https://openalex.org/W2088203270","https://openalex.org/W2100882222","https://openalex.org/W2109755562","https://openalex.org/W2112036221","https://openalex.org/W2118158907","https://openalex.org/W2136734237","https://openalex.org/W2138908842","https://openalex.org/W2141776905","https://openalex.org/W2163532598","https://openalex.org/W2493676419","https://openalex.org/W2766736793","https://openalex.org/W3017143921","https://openalex.org/W4242427575","https://openalex.org/W4244194021","https://openalex.org/W4246951696","https://openalex.org/W4247282788","https://openalex.org/W6631831516","https://openalex.org/W6652063971","https://openalex.org/W6672596321","https://openalex.org/W6682610290","https://openalex.org/W6684375713"],"related_works":["https://openalex.org/W2155285526","https://openalex.org/W2394022884","https://openalex.org/W2185815555","https://openalex.org/W2071235072","https://openalex.org/W1924227955","https://openalex.org/W4242258007","https://openalex.org/W2007222089","https://openalex.org/W1917800633","https://openalex.org/W2044302877","https://openalex.org/W311401163"],"abstract_inverted_index":{"This":[0],"paper":[1,37],"presents":[2],"a":[3,25],"new":[4],"technique":[5,40],"for":[6,41,56,59,93],"automatically":[7,64],"creating":[8],"analog":[9],"circuit":[10,31,44,48],"models.":[11],"The":[12,36],"method":[13],"extracts":[14],"piecewise":[15],"linear":[16,28],"models":[17,58,71,90],"from":[18],"trained":[19,86],"neural":[20,87],"networks.":[21,88],"A":[22],"model":[23],"is":[24],"set":[26],"of":[27,84,96],"dependencies":[29],"between":[30],"performances":[32],"and":[33,53,61,81,101],"design":[34],"parameters.":[35],"illustrates":[38],"the":[39,69,78,82,85],"an":[42,46],"OTA":[43],"-":[45],"amplifier":[47],"widely":[49],"used":[50],"in":[51],"filters":[52],"A/D":[54],"converters":[55],"which":[57],"gain":[60],"bandwidth":[62],"were":[63],"generated.":[65],"As":[66],"experiments":[67],"show,":[68],"obtained":[70],"have":[72],"simple":[73],"form":[74],"that":[75],"accurately":[76],"fits":[77],"sampled":[79],"points":[80],"behavior":[83,100],"These":[89],"are":[91],"useful":[92],"fast":[94],"simulation":[95],"systems":[97],"with":[98],"non-linear":[99],"performances.":[102]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
