{"id":"https://openalex.org/W2153262065","doi":"https://doi.org/10.1109/ijcnn.2003.1223820","title":"A model-selection approach to the VLSI design of vector quantizers","display_name":"A model-selection approach to the VLSI design of vector quantizers","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W2153262065","doi":"https://doi.org/10.1109/ijcnn.2003.1223820","mag":"2153262065"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2003.1223820","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2003.1223820","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Joint Conference on Neural Networks, 2003.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053303939","display_name":"M. Bracco","orcid":null},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Bracco","raw_affiliation_strings":["DIBE-Department Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIBE-Department Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072692847","display_name":"Sandro Ridella","orcid":"https://orcid.org/0000-0003-0612-8219"},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Ridella","raw_affiliation_strings":["DIBE-Department Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIBE-Department Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103049522","display_name":"Rodolfo Zunino","orcid":"https://orcid.org/0000-0002-2150-7076"},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Zunino","raw_affiliation_strings":["DIBE-Department Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIBE-Department Biophysical and Electronic Engineering, University of Genoa, Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I83816512"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20831055,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"959","last_page":"964"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9860000014305115,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9850999712944031,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7308893799781799},{"id":"https://openalex.org/keywords/vector-quantization","display_name":"Vector quantization","score":0.6900263428688049},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6851311922073364},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6018184423446655},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.5503647923469543},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.5430289506912231},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4615696668624878},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4424666464328766},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4389500617980957},{"id":"https://openalex.org/keywords/consistency","display_name":"Consistency (knowledge bases)","score":0.4369821846485138},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4300363063812256},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3907909393310547},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3043826222419739},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2958800196647644},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20249786972999573},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17441481351852417},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07902795076370239}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7308893799781799},{"id":"https://openalex.org/C199833920","wikidata":"https://www.wikidata.org/wiki/Q612536","display_name":"Vector quantization","level":2,"score":0.6900263428688049},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6851311922073364},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6018184423446655},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.5503647923469543},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.5430289506912231},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4615696668624878},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4424666464328766},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4389500617980957},{"id":"https://openalex.org/C2776436953","wikidata":"https://www.wikidata.org/wiki/Q5163215","display_name":"Consistency (knowledge bases)","level":2,"score":0.4369821846485138},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4300363063812256},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3907909393310547},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3043826222419739},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2958800196647644},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20249786972999573},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17441481351852417},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07902795076370239},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ijcnn.2003.1223820","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2003.1223820","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Joint Conference on Neural Networks, 2003.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1634005169","https://openalex.org/W1991848143","https://openalex.org/W2097922162","https://openalex.org/W2106596127","https://openalex.org/W2124885662","https://openalex.org/W2126580827","https://openalex.org/W2135326240","https://openalex.org/W2142635246","https://openalex.org/W2154439236","https://openalex.org/W2156392572","https://openalex.org/W2170663320"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W3209251257","https://openalex.org/W2232520249","https://openalex.org/W3183118997","https://openalex.org/W3214410901","https://openalex.org/W3204400881","https://openalex.org/W3204296682","https://openalex.org/W2917767146","https://openalex.org/W2800543810","https://openalex.org/W2082756771"],"abstract_inverted_index":{"A":[0,14],"formal":[1],"methodology":[2],"supports":[3],"the":[4,19,36,55,58,62,65],"design":[5],"of":[6,57,64],"digital":[7,38],"services":[8],"for":[9],"hierarchical":[10],"vector":[11],"quantization":[12],"(HVQ).":[13],"model-selection":[15],"approach":[16,60],"based":[17],"on":[18],"minimum":[20],"description":[21],"length":[22],"criterion":[23],"is":[24],"enhanced":[25],"by":[26],"circuit-related":[27],"aspects":[28],"allowing":[29],"efficient":[30,49],"design.":[31],"The":[32],"resulting":[33],"parameters":[34],"drive":[35],"subsequent":[37],"VLSI":[39],"realization,":[40],"which":[41],"yields":[42],"a":[43],"HVQ":[44,66],"chip":[45],"providing":[46],"cost-effective,":[47],"computationally":[48],"real-time":[50],"performances.":[51],"Real-world":[52],"applications":[53],"support":[54],"consistency":[56],"VQ":[59],"and":[61],"effectiveness":[63],"device.":[67]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
