{"id":"https://openalex.org/W3012219827","doi":"https://doi.org/10.1109/iiswc47752.2019.9042051","title":"Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior","display_name":"Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W3012219827","doi":"https://doi.org/10.1109/iiswc47752.2019.9042051","mag":"3012219827"},"language":"en","primary_location":{"id":"doi:10.1109/iiswc47752.2019.9042051","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iiswc47752.2019.9042051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Workload Characterization (IISWC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043375025","display_name":"Alexander Hankin","orcid":null},"institutions":[{"id":"https://openalex.org/I121934306","display_name":"Tufts University","ror":"https://ror.org/05wvpxv85","country_code":"US","type":"education","lineage":["https://openalex.org/I121934306"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alexander Hankin","raw_affiliation_strings":["Tufts University,Department of Electrical and Computer Engineering","Department of Electrical and Computer Engineering, Tufts University"],"affiliations":[{"raw_affiliation_string":"Tufts University,Department of Electrical and Computer Engineering","institution_ids":["https://openalex.org/I121934306"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Tufts University","institution_ids":["https://openalex.org/I121934306"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044014334","display_name":"Tomer Shapira","orcid":null},"institutions":[{"id":"https://openalex.org/I121934306","display_name":"Tufts University","ror":"https://ror.org/05wvpxv85","country_code":"US","type":"education","lineage":["https://openalex.org/I121934306"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tomer Shapira","raw_affiliation_strings":["Tufts University,Department of Electrical and Computer Engineering","Department of Electrical and Computer Engineering, Tufts University"],"affiliations":[{"raw_affiliation_string":"Tufts University,Department of Electrical and Computer Engineering","institution_ids":["https://openalex.org/I121934306"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Tufts University","institution_ids":["https://openalex.org/I121934306"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035895394","display_name":"Karthik Sangaiah","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Karthik Sangaiah","raw_affiliation_strings":["Drexel University,Department of Electrical and Computer Engineering","Department of Electrical and Computer Engineering, Drexel University"],"affiliations":[{"raw_affiliation_string":"Drexel University,Department of Electrical and Computer Engineering","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030604482","display_name":"Michael Lui","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Lui","raw_affiliation_strings":["Drexel University,Department of Electrical and Computer Engineering","Department of Electrical and Computer Engineering, Drexel University"],"affiliations":[{"raw_affiliation_string":"Drexel University,Department of Electrical and Computer Engineering","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018352758","display_name":"Mark Hempstead","orcid":"https://orcid.org/0000-0001-9696-4741"},"institutions":[{"id":"https://openalex.org/I121934306","display_name":"Tufts University","ror":"https://ror.org/05wvpxv85","country_code":"US","type":"education","lineage":["https://openalex.org/I121934306"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Hempstead","raw_affiliation_strings":["Tufts University,Department of Electrical and Computer Engineering","Department of Electrical and Computer Engineering, Tufts University"],"affiliations":[{"raw_affiliation_string":"Tufts University,Department of Electrical and Computer Engineering","institution_ids":["https://openalex.org/I121934306"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Tufts University","institution_ids":["https://openalex.org/I121934306"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5043375025"],"corresponding_institution_ids":["https://openalex.org/I121934306"],"apc_list":null,"apc_paid":null,"fwci":0.4769,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.66967869,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"143","last_page":"154"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7730284929275513},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7087994813919067},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.638679027557373},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6259890794754028},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5963156223297119},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.5751217603683472},{"id":"https://openalex.org/keywords/working-set","display_name":"Working set","score":0.5679126977920532},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.4712013900279999},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.44692346453666687},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3558019995689392},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3519638180732727},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33767199516296387},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.26850420236587524},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.25450968742370605},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20050567388534546},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1598125696182251},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.1329357624053955},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09841963648796082}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7730284929275513},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7087994813919067},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.638679027557373},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6259890794754028},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5963156223297119},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.5751217603683472},{"id":"https://openalex.org/C88196245","wikidata":"https://www.wikidata.org/wiki/Q8034984","display_name":"Working set","level":2,"score":0.5679126977920532},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.4712013900279999},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.44692346453666687},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3558019995689392},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3519638180732727},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33767199516296387},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.26850420236587524},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.25450968742370605},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20050567388534546},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1598125696182251},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.1329357624053955},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09841963648796082},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iiswc47752.2019.9042051","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iiswc47752.2019.9042051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Workload Characterization (IISWC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":61,"referenced_works":["https://openalex.org/W35708471","https://openalex.org/W1506854048","https://openalex.org/W1532969923","https://openalex.org/W1568580058","https://openalex.org/W1573873562","https://openalex.org/W1963958751","https://openalex.org/W1966058111","https://openalex.org/W1971236076","https://openalex.org/W1979955706","https://openalex.org/W2003284017","https://openalex.org/W2005917534","https://openalex.org/W2009387496","https://openalex.org/W2010202670","https://openalex.org/W2013028205","https://openalex.org/W2014895289","https://openalex.org/W2034062945","https://openalex.org/W2036853599","https://openalex.org/W2041420601","https://openalex.org/W2041610138","https://openalex.org/W2054589004","https://openalex.org/W2063799733","https://openalex.org/W2075278406","https://openalex.org/W2075960179","https://openalex.org/W2084007230","https://openalex.org/W2087339326","https://openalex.org/W2097336080","https://openalex.org/W2112121929","https://openalex.org/W2116826022","https://openalex.org/W2127419525","https://openalex.org/W2128968239","https://openalex.org/W2137598681","https://openalex.org/W2138449721","https://openalex.org/W2149412112","https://openalex.org/W2155551886","https://openalex.org/W2156560114","https://openalex.org/W2157587823","https://openalex.org/W2160996172","https://openalex.org/W2169875292","https://openalex.org/W2290121533","https://openalex.org/W2290824897","https://openalex.org/W2329141363","https://openalex.org/W2510186576","https://openalex.org/W2515080096","https://openalex.org/W2516639415","https://openalex.org/W2532453544","https://openalex.org/W2572697907","https://openalex.org/W2606951540","https://openalex.org/W2805103555","https://openalex.org/W2884574523","https://openalex.org/W2964330541","https://openalex.org/W3006039064","https://openalex.org/W3037934120","https://openalex.org/W3105753409","https://openalex.org/W3106468038","https://openalex.org/W4232092075","https://openalex.org/W4245080405","https://openalex.org/W4249654426","https://openalex.org/W6674334183","https://openalex.org/W6680415081","https://openalex.org/W6683184104","https://openalex.org/W6731628220"],"related_works":["https://openalex.org/W2149765501","https://openalex.org/W2147578077","https://openalex.org/W4293261839","https://openalex.org/W1997464441","https://openalex.org/W2088805041","https://openalex.org/W4243453130","https://openalex.org/W2246887984","https://openalex.org/W4240163901","https://openalex.org/W4387141464","https://openalex.org/W3012219827"],"abstract_inverted_index":{"To":[0],"confront":[1],"the":[2,9,29,39,83,92,109,117,125,142,243,318],"memory":[3],"wall":[4],"and":[5,51,101,121,172,184,197,200,225,238,245,267,323,334,344],"keep":[6,114],"up":[7,74,115,286],"with":[8,64,91,116,169,189,258,328,341],"demands":[10],"of":[11,43,87,94,128,177,204,218,247,290,295],"changing":[12],"use":[13,88,181,205,254,284,320],"cases,":[14,69,321],"Non-Volatile":[15],"Memories":[16],"(NVMs)":[17],"have":[18],"begun":[19],"to":[20,57,75,108,113,138,156,287],"be":[21,139],"considered":[22],"as":[23],"a":[24,147,165,216,227,248],"replacement":[25],"for":[26,72,119,149,220,252,317],"SRAM":[27],"in":[28],"Last":[30],"Level":[31],"Cache":[32],"(LLC).":[33],"Recent":[34],"work":[35,209,260],"has":[36],"shown":[37],"that":[38,136,231,280,294,316],"small":[40],"cell":[41,265],"size":[42,86],"NVMs":[44,163],"like":[45,236],"Spin-":[46],"Torque":[47],"Transfer":[48],"RAM":[49,53],"(STTRAM)":[50],"Resistive":[52],"(RRAM)":[54],"allows":[55,71],"designers":[56],"build":[58],"significantly":[59],"denser":[60],"LLCs":[61],"than":[62,80,293],"those":[63],"SRAM-based":[65,297],"cells.":[66],"In":[67,207,256],"some":[68],"this":[70,178,208,259],"storing":[73],"10\u00d7":[76],"more":[77,105],"data":[78],"on-chip":[79],"before.":[81],"As":[82],"working":[84,239],"set":[85,217,240],"cases":[89],"increases":[90],"advent":[93],"statistical":[95],"inference":[96],"(e.g.,":[97],"machine":[98],"learning":[99],"(ML)":[100],"artificial":[102],"intelligence":[103],"(AI)),":[104],"capacity":[106],"close":[107],"processor":[110],"is":[111,145,285,305],"necessary":[112],"demand":[118],"performance":[120,183,244],"low":[122],"power.":[123],"Despite":[124],"growing":[126],"potential":[127],"NVM-based":[129,160,223,249,275,281],"LLCs,":[130,224],"there":[131],"are":[132,186,325],"still":[133],"fundamental":[134],"problems":[135],"need":[137],"addressed.":[140],"First,":[141],"research":[143],"community":[144],"lacking":[146],"methodology":[148],"consistently":[150],"modeling":[151,221],"these":[152],"devices,":[153],"which":[154],"leads":[155],"apples-to-oranges":[157],"comparisons":[158],"across":[159],"LLCs.":[161],"Second,":[162],"exhibit":[164],"key":[166],"operational":[167],"difference":[168],"SRAM:":[170],"read":[171,196,343],"write":[173,198,329,332,336,345],"asymmetry.":[174],"The":[175],"effects":[176],"asymmetry":[179],"on":[180,194,201,307],"case":[182],"power":[185,246],"mostly":[187],"unknown":[188],"prior":[190],"art":[191],"relying":[192],"only":[193],"total":[195,342],"counts":[199],"limited":[202],"sets":[203],"cases.":[206,255],"we":[210,261,278,314],"present":[211],"two":[212],"novel":[213],"contributions:":[214],"(1)":[215],"heuristics":[219],"emerging":[222],"(2)":[226],"workload":[228,311],"characterization":[229,312],"framework":[230],"learns":[232],"how":[233],"architecture-agnostic":[234],"features,":[235],"entropy":[237],"size,":[241],"affect":[242],"LLC":[250,276,282,298],"system":[251],"different":[253],"addition,":[257],"release":[262],"our":[263,274,310],"NVM":[264],"models":[266,277],"make":[268],"them":[269],"publicly":[270],"available":[271],"online.":[272],"Using":[273],"show":[279,315],"energy":[283,322],"an":[288,296],"order":[289],"magnitude":[291],"less":[292],"while":[299,338],"ED":[300],"<sup":[301],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[302],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[303],"p":[304],"generally":[306],"par.":[308],"From":[309],"framework,":[313],"AI":[319],"speedup":[324],"99%":[326],"correlated":[327,340],"entropy,":[330],"90%":[331],"footprint,":[333],"unique":[335],"footprint":[337],"negligibly":[339],"footprint.":[346]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}