{"id":"https://openalex.org/W2528472514","doi":"https://doi.org/10.1109/iiswc.2016.7581279","title":"Memory controller design under cloud workloads","display_name":"Memory controller design under cloud workloads","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2528472514","doi":"https://doi.org/10.1109/iiswc.2016.7581279","mag":"2528472514"},"language":"en","primary_location":{"id":"doi:10.1109/iiswc.2016.7581279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iiswc.2016.7581279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Workload Characterization (IISWC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/1611.10316","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Mostafa Mahmoud","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Mostafa Mahmoud","raw_affiliation_strings":["Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":null,"display_name":"Andreas Moshovos","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andreas Moshovos","raw_affiliation_strings":["Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10913263,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7325000166893005},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6323000192642212},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5976999998092651},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5769000053405762},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.5347999930381775},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.517799973487854},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.48190000653266907},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4431999921798706},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.41589999198913574},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4074999988079071}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7581999897956848},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7325000166893005},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6323000192642212},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5976999998092651},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5769000053405762},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.5347999930381775},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.517799973487854},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.48190000653266907},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4431999921798706},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.41589999198913574},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4074999988079071},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.3736000061035156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37310001254081726},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.36070001125335693},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.3538999855518341},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.34470000863075256},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3433000147342682},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3034999966621399},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.30250000953674316},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.30070000886917114},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.30000001192092896},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.2985000014305115},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.29580000042915344},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.28529998660087585},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2833000123500824},{"id":"https://openalex.org/C79974875","wikidata":"https://www.wikidata.org/wiki/Q483639","display_name":"Cloud computing","level":2,"score":0.2786000072956085},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.2770000100135803},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.27399998903274536},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.27059999108314514},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.2696000039577484},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.26499998569488525},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.2639999985694885},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.25130000710487366}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iiswc.2016.7581279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iiswc.2016.7581279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Workload Characterization (IISWC)","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:1611.10316","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1611.10316","pdf_url":"https://arxiv.org/pdf/1611.10316","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:1611.10316","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1611.10316","pdf_url":"https://arxiv.org/pdf/1611.10316","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1498525413","https://openalex.org/W2025304002","https://openalex.org/W2036853599","https://openalex.org/W2054319838","https://openalex.org/W2056200836","https://openalex.org/W2065439108","https://openalex.org/W2096864363","https://openalex.org/W2100787464","https://openalex.org/W2102871765","https://openalex.org/W2115172404","https://openalex.org/W2117816012","https://openalex.org/W2128315927","https://openalex.org/W2132269953","https://openalex.org/W2140980291","https://openalex.org/W2141181087","https://openalex.org/W2144857621","https://openalex.org/W2155371841","https://openalex.org/W2159908132","https://openalex.org/W2162838417","https://openalex.org/W2164264749","https://openalex.org/W2175973557","https://openalex.org/W3150859138","https://openalex.org/W4238549726","https://openalex.org/W6630265792","https://openalex.org/W6641191176","https://openalex.org/W6693918034","https://openalex.org/W6793277613"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"studies":[2],"the":[3,23,29,69,72,85],"behavior":[4],"of":[5,25,68,81,87,108,126],"state-of-the-art":[6],"memory":[7,16,19,26,41,88,127],"controller":[8],"designs":[9],"when":[10],"executing":[11],"scale-out":[12,51,130],"workloads.":[13,52,131],"It":[14],"considers":[15],"scheduling":[17,42,76],"techniques,":[18],"page":[20],"management":[21],"policies,":[22],"number":[24,86],"channels,":[27],"and":[28,64,124],"address":[30],"mapping":[31],"scheme":[32],"used.":[33],"Experimental":[34],"measurements":[35],"demonstrate:":[36],"1)":[37],"Several":[38],"recently":[39],"proposed":[40],"policies":[43],"are":[44,112],"not":[45],"a":[46],"good":[47],"match":[48],"for":[49,66,101,129],"these":[50],"2)":[53],"The":[54],"relatively":[55],"simple":[56],"First-Ready-First-Come-":[57],"First-Served":[58],"(FR-FCFS)":[59],"policy":[60,77],"performs":[61],"consistently":[62],"better,":[63],"3)":[65],"most":[67],"studied":[70],"workloads,":[71],"even":[73],"simpler":[74],"First-Come-First-Served":[75],"is":[78],"within":[79],"1%":[80],"FRFCFS.":[82],"4)":[83],"Increasing":[84],"channels":[89],"offers":[90],"negligible":[91],"performance":[92,95],"benefits,":[93],"e.g.,":[94],"improves":[96],"by":[97],"1.7%":[98],"on":[99],"average":[100],"4-channels":[102],"vs.":[103],"1-channel.":[104],"5)":[105],"77%-":[106],"90%":[107],"DRAM":[109],"rows":[110],"activations":[111],"accessed":[113],"only":[114],"once":[115],"before":[116],"closure.":[117],"These":[118],"observation":[119],"can":[120],"guide":[121],"future":[122],"development":[123],"optimization":[125],"controllers":[128]},"counts_by_year":[],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2016-10-14T00:00:00"}