{"id":"https://openalex.org/W2954620240","doi":"https://doi.org/10.1109/igcc.2018.8752126","title":"Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery","display_name":"Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2954620240","doi":"https://doi.org/10.1109/igcc.2018.8752126","mag":"2954620240"},"language":"en","primary_location":{"id":"doi:10.1109/igcc.2018.8752126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/igcc.2018.8752126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103072785","display_name":"MD Shazzad Hossain","orcid":"https://orcid.org/0000-0002-7689-7526"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"MD Shazzad Hossain","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059641297","display_name":"Ioannis Savidis","orcid":"https://orcid.org/0000-0003-4230-1795"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ioannis Savidis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":0.7793,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71059196,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8151942491531372},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.7702609896659851},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7251737117767334},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7023424506187439},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6905134320259094},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6226829290390015},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5219770669937134},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5168312191963196},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5135812759399414},{"id":"https://openalex.org/keywords/cpu-core-voltage","display_name":"CPU core voltage","score":0.507227897644043},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4913384020328522},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.4483170509338379},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4392993450164795},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.33697617053985596},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30605149269104004},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27596890926361084},{"id":"https://openalex.org/keywords/voltage-regulation","display_name":"Voltage regulation","score":0.2045261561870575},{"id":"https://openalex.org/keywords/voltage-optimisation","display_name":"Voltage optimisation","score":0.16559231281280518},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10025417804718018},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09262219071388245}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8151942491531372},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.7702609896659851},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7251737117767334},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7023424506187439},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6905134320259094},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6226829290390015},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5219770669937134},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5168312191963196},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5135812759399414},{"id":"https://openalex.org/C55038917","wikidata":"https://www.wikidata.org/wiki/Q453979","display_name":"CPU core voltage","level":5,"score":0.507227897644043},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4913384020328522},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.4483170509338379},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4392993450164795},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.33697617053985596},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30605149269104004},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27596890926361084},{"id":"https://openalex.org/C196226539","wikidata":"https://www.wikidata.org/wiki/Q7940752","display_name":"Voltage regulation","level":3,"score":0.2045261561870575},{"id":"https://openalex.org/C46529443","wikidata":"https://www.wikidata.org/wiki/Q7940750","display_name":"Voltage optimisation","level":4,"score":0.16559231281280518},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10025417804718018},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09262219071388245}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/igcc.2018.8752126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/igcc.2018.8752126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1499762250","https://openalex.org/W1968721941","https://openalex.org/W1972573758","https://openalex.org/W1982199193","https://openalex.org/W1993093542","https://openalex.org/W2006969207","https://openalex.org/W2034182926","https://openalex.org/W2056539138","https://openalex.org/W2065045880","https://openalex.org/W2090853900","https://openalex.org/W2111880608","https://openalex.org/W2122309939","https://openalex.org/W2125857172","https://openalex.org/W2168159483","https://openalex.org/W2170331607","https://openalex.org/W2213419840","https://openalex.org/W2220643768","https://openalex.org/W2306785259","https://openalex.org/W2511749978","https://openalex.org/W2591811992","https://openalex.org/W2672631140","https://openalex.org/W2759380705","https://openalex.org/W2788706082","https://openalex.org/W2802291603","https://openalex.org/W4243164749","https://openalex.org/W4253421865"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2090213929","https://openalex.org/W2617666058","https://openalex.org/W2165139624","https://openalex.org/W2144282137","https://openalex.org/W2803012234","https://openalex.org/W3006003651","https://openalex.org/W2127892766"],"abstract_inverted_index":{"In":[0,136],"this":[1],"paper,":[2],"the":[3,6,37,52,138,153,157,169],"co-design":[4],"of":[5,51],"clock":[7,38,46,53,104,130,140,171],"and":[8,26,41,59,66,77,87,93,107,116,126,141,161],"power":[9,16,28,142,163],"delivery":[10],"networks":[11,143],"is":[12,31,80,166],"proposed":[13,32,158],"for":[14,82],"ultra-low":[15],"IoT":[17],"applications":[18],"operating":[19,85],"in":[20,44,96,152],"sub-threshold.":[21],"A":[22],"distributed,":[23],"multi-voltage":[24,159],"domain":[25,160],"hierarchical":[27],"distribution":[29,47,164],"network":[30,131,165],"to":[33,36,75,128,146],"deliver":[34],"current":[35],"buffers,":[39],"registers,":[40],"combinational":[42],"circuits":[43],"local":[45],"networks.":[48],"The":[49,70,102],"variation":[50,79,151],"skew,":[54,106],"setup":[55],"time,":[56,58],"hold":[57],"clock-to-q":[60],"delay":[61,109],"are":[62,110,122],"analyzed":[63,81],"under":[64],"process":[65,78],"supply":[67,76,154],"voltage":[68,86,155],"variation.":[69],"effect":[71],"on":[72],"timing":[73],"due":[74],"a":[83,97,129],"target":[84],"frequency":[88],"of,":[89],"respectively,":[90,113],"250":[91],"mV":[92],"2":[94],"MHz":[95],"130":[98],"nm":[99],"CMOS":[100],"technology.":[101],"minimum":[103],"period,":[105],"insertion":[108],"reduced":[111],"to,":[112],"0.74\u00d7,":[114],"0.52\u00d7,":[115],"0.79\u00d7":[117],"when":[118,156],"optimized":[119,170],"sub-threshold":[120],"buffers":[121],"implemented,":[123],"as":[124,147,149],"compared":[125],"normalized":[127],"that":[132],"includes":[133],"non-optimized":[134],"buffers.":[135,172],"addition,":[137],"co-designed":[139],"were":[144],"resilient":[145],"much":[148],"10%":[150],"distributed":[162],"used":[167],"with":[168]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}