{"id":"https://openalex.org/W2044358145","doi":"https://doi.org/10.1109/igcc.2011.6008604","title":"Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime","display_name":"Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2044358145","doi":"https://doi.org/10.1109/igcc.2011.6008604","mag":"2044358145"},"language":"en","primary_location":{"id":"doi:10.1109/igcc.2011.6008604","is_oa":false,"landing_page_url":"https://doi.org/10.1109/igcc.2011.6008604","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Green Computing Conference and Workshops","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063749282","display_name":"Joseph Crop","orcid":null},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Joseph Crop","raw_affiliation_strings":["School of EECS, Oregon State University, Corvallis, OR, USA","School of EECS, Oregon State University, Corvallis, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, OR, USA","institution_ids":["https://openalex.org/I131249849"]},{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, USA#TAB#","institution_ids":["https://openalex.org/I131249849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034651290","display_name":"Robert Paw\u0142owski","orcid":null},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Pawlowski","raw_affiliation_strings":["School of EECS, Oregon State University, Corvallis, OR, USA","School of EECS, Oregon State University, Corvallis, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, OR, USA","institution_ids":["https://openalex.org/I131249849"]},{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, USA#TAB#","institution_ids":["https://openalex.org/I131249849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019080918","display_name":"Nariman Moezzi-Madani","orcid":null},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nariman Moezzi-Madani","raw_affiliation_strings":["School of EECS, Oregon State University, Corvallis, OR, USA","School of EECS, Oregon State University, Corvallis, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, OR, USA","institution_ids":["https://openalex.org/I131249849"]},{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, USA#TAB#","institution_ids":["https://openalex.org/I131249849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065134319","display_name":"J. Jackson","orcid":null},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jarrod Jackson","raw_affiliation_strings":["School of EECS, Oregon State University, Corvallis, OR, USA","School of EECS, Oregon State University, Corvallis, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, OR, USA","institution_ids":["https://openalex.org/I131249849"]},{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, USA#TAB#","institution_ids":["https://openalex.org/I131249849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077202301","display_name":"Patrick Chaing","orcid":null},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Chaing","raw_affiliation_strings":["School of EECS, Oregon State University, Corvallis, OR, USA","School of EECS, Oregon State University, Corvallis, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, OR, USA","institution_ids":["https://openalex.org/I131249849"]},{"raw_affiliation_string":"School of EECS, Oregon State University, Corvallis, USA#TAB#","institution_ids":["https://openalex.org/I131249849"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5063749282"],"corresponding_institution_ids":["https://openalex.org/I131249849"],"apc_list":null,"apc_paid":null,"fwci":1.0599,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.79326995,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"3","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.8078947067260742},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6848046183586121},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6052227020263672},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5996397137641907},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5692634582519531},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5603543519973755},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.534339189529419},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5053930282592773},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48771461844444275},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.47891342639923096},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47538483142852783},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.46568527817726135},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.454891175031662},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.44027209281921387},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4351705014705658},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41940760612487793},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4139770269393921},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36980193853378296},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.34880518913269043},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3044555187225342},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2576373815536499},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24296945333480835},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19725123047828674},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14898642897605896},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1155499517917633}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.8078947067260742},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6848046183586121},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6052227020263672},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5996397137641907},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5692634582519531},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5603543519973755},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.534339189529419},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5053930282592773},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48771461844444275},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.47891342639923096},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47538483142852783},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.46568527817726135},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.454891175031662},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.44027209281921387},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4351705014705658},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41940760612487793},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4139770269393921},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36980193853378296},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.34880518913269043},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3044555187225342},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2576373815536499},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24296945333480835},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19725123047828674},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14898642897605896},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1155499517917633},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/igcc.2011.6008604","is_oa":false,"landing_page_url":"https://doi.org/10.1109/igcc.2011.6008604","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Green Computing Conference and Workshops","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W649475307","https://openalex.org/W1491082069","https://openalex.org/W1499762250","https://openalex.org/W1607087355","https://openalex.org/W1967171495","https://openalex.org/W2046425517","https://openalex.org/W2066384074","https://openalex.org/W2087107264","https://openalex.org/W2106050980","https://openalex.org/W2108312065","https://openalex.org/W2123783696","https://openalex.org/W2129439881","https://openalex.org/W2139542266","https://openalex.org/W2156638740","https://openalex.org/W2167448582","https://openalex.org/W2169766445","https://openalex.org/W2542641152","https://openalex.org/W3142442347","https://openalex.org/W4230854430"],"related_works":["https://openalex.org/W2171793444","https://openalex.org/W3211857759","https://openalex.org/W2066616140","https://openalex.org/W2135308224","https://openalex.org/W2337636225","https://openalex.org/W2045408571","https://openalex.org/W2060392256","https://openalex.org/W2349227977","https://openalex.org/W1596716095","https://openalex.org/W2031753133"],"abstract_inverted_index":{"Ultra-low":[0],"power":[1],"digital":[2,26],"circuit":[3,27],"design":[4,35,55,125],"using":[5],"sub-threshold":[6,31,71],"supply":[7],"voltages":[8],"has":[9],"recently":[10],"been":[11],"popularized":[12],"for":[13,45,66,88],"energy-constrained":[14],"systems,":[15],"sensor":[16],"networks":[17],"and":[18,43,96,113],"bio-sensor":[19],"applications.":[20],"The":[21,78],"conventional":[22],"method":[23],"to":[24,34],"improve":[25],"operation":[28,68,87],"in":[29,61,69],"the":[30,70,120],"region":[32],"is":[33,84],"every":[36,46,59],"logic":[37],"cell":[38,60,64,91,123],"manually,":[39],"requiring":[40],"complete":[41],"re-design":[42],"re-characterization":[44],"process":[47,83],"node.":[48],"This":[49],"proposed":[50],"work":[51],"introduces":[52],"a":[53,62,102,127],"computational":[54],"automation":[56],"that":[57,75],"tests":[58],"standard":[63,90,122],"library":[65,124],"proper":[67],"region,":[72],"eliminating":[73],"cells":[74],"perform":[76],"poorly.":[77],"result":[79],"of":[80,101,119],"this":[81],"culling":[82],"improved":[85,108],"sub-/near-threshold":[86],"any":[89],"library,":[92],"improving":[93],"delay,":[94],"area,":[95],"energy.":[97],"Monte-Carlo":[98],"simulation":[99],"results":[100],"synthesized":[103,129],"90nm-CMOS":[104],"Floating-Point":[105],"Adder":[106],"verifies":[107],"mean":[109],"timing":[110],"delay":[111],"(32%)":[112],"overall":[114],"energy":[115],"per":[116],"computation":[117],"(37%)":[118],"culled":[121],"over":[126],"regular":[128],"design.":[130]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
