{"id":"https://openalex.org/W7140580683","doi":"https://doi.org/10.1109/ieeeconf67917.2025.11443783","title":"Exploring the Limits of High-Throughput Wideband Digital Signal Processing on AMD Versal AI Engines and Programmable Logic: Insights from a Polyphase Filter Bank Deployment","display_name":"Exploring the Limits of High-Throughput Wideband Digital Signal Processing on AMD Versal AI Engines and Programmable Logic: Insights from a Polyphase Filter Bank Deployment","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W7140580683","doi":"https://doi.org/10.1109/ieeeconf67917.2025.11443783"},"language":null,"primary_location":{"id":"doi:10.1109/ieeeconf67917.2025.11443783","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ieeeconf67917.2025.11443783","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 59th Asilomar Conference on Signals, Systems, and Computers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025551731","display_name":"Simone Acciarito","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Simone Acciarito","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gian Carlo Cardarilli","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112024187","display_name":"Luca Di Nunzio","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Di Nunzio","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093362636","display_name":"Riccardo La Cesa","orcid":"https://orcid.org/0009-0001-4978-4921"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Riccardo La Cesa","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130640627","display_name":"Marco Re","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Re","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130649761","display_name":"Sergio Span\u00f2","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sergio Span\u00f2","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066999166","display_name":"C.F. Valenti","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristian Valenti","raw_affiliation_strings":["Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Tor Vergata University,Dept. of Electronic Eng.,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5025551731"],"corresponding_institution_ids":["https://openalex.org/I116067653"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.80715851,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"285","last_page":"289"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.1873999983072281,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.1873999983072281,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.04899999871850014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12131","display_name":"Wireless Signal Modulation Classification","score":0.04450000077486038,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/polyphase-system","display_name":"Polyphase system","score":0.8151999711990356},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.5763999819755554},{"id":"https://openalex.org/keywords/filter-bank","display_name":"Filter bank","score":0.5091000199317932},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.49709999561309814},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.4717000126838684},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4697999954223633},{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.4180000126361847}],"concepts":[{"id":"https://openalex.org/C96157337","wikidata":"https://www.wikidata.org/wiki/Q391639","display_name":"Polyphase system","level":2,"score":0.8151999711990356},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6291999816894531},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.5763999819755554},{"id":"https://openalex.org/C100515483","wikidata":"https://www.wikidata.org/wiki/Q3268235","display_name":"Filter bank","level":3,"score":0.5091000199317932},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.49709999561309814},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4781000018119812},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.4717000126838684},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4697999954223633},{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.4180000126361847},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36070001125335693},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.3481999933719635},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.3264999985694885},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.30959999561309814},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.2962999939918518},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.290800005197525},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.28529998660087585},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2809000015258789},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2775999903678894},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25429999828338623},{"id":"https://openalex.org/C147788027","wikidata":"https://www.wikidata.org/wiki/Q2718101","display_name":"Band-pass filter","level":2,"score":0.25200000405311584}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ieeeconf67917.2025.11443783","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ieeeconf67917.2025.11443783","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 59th Asilomar Conference on Signals, Systems, and Computers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W3143599535","https://openalex.org/W4400275668","https://openalex.org/W4403279027","https://openalex.org/W4404955704","https://openalex.org/W4413144302","https://openalex.org/W4413211482","https://openalex.org/W4414197095","https://openalex.org/W4414198091"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"explores":[2],"the":[3,6,57,92,98,104,116],"capabilities":[4],"of":[5,21,24,100],"new":[7],"AMD":[8,69],"Versal":[9],"AI":[10,38,82],"Engines":[11],"for":[12],"wideband":[13],"digital":[14],"signal":[15],"processing.":[16],"We":[17],"present":[18],"a":[19,25,87,111],"proof":[20],"concept":[22],"comparison":[23],"Polyphase":[26],"Filter":[27],"Bank":[28],"architecture":[29],"deployed":[30],"both":[31],"on":[32,37,67],"Programmable":[33],"Logic":[34],"(PL)":[35],"and":[36,50],"Engines.":[39],"The":[40,81,107],"goal":[41],"is":[42],"to":[43,77],"evaluate":[44],"metrics":[45],"such":[46],"as":[47],"maximum":[48],"bandwidth":[49,89],"power":[51,105],"dissipation,":[52],"assessing":[53],"which":[54],"implementation":[55],"offers":[56],"best":[58],"performance":[59,117],"under":[60],"system":[61],"constraints.":[62],"Both":[63],"systems":[64],"were":[65],"implemented":[66],"an":[68],"VCK190":[70],"evaluation":[71],"board,":[72],"with":[73],"resource":[74],"utilization":[75],"maximized":[76],"achieve":[78],"peak":[79],"performance.":[80],"Engine":[83],"based":[84,94],"design":[85],"achieves":[86],"90%":[88],"improvement":[90],"over":[91],"PL":[93],"implementation,":[95],"albeit":[96],"at":[97],"cost":[99],"more":[101],"than":[102],"doubling":[103],"consumption.":[106],"results":[108],"demonstrate":[109],"that":[110],"single":[112],"device":[113],"can":[114],"match":[115],"levels":[118],"typically":[119],"requiring":[120],"multiple":[121],"FPGA":[122],"systems.":[123]},"counts_by_year":[],"updated_date":"2026-03-28T06:11:35.319607","created_date":"2026-03-27T00:00:00"}
