{"id":"https://openalex.org/W4415968559","doi":"https://doi.org/10.1109/iecon58223.2025.11221130","title":"Low-Latency Serial-to-Parallel Conversion for Feedback Shift Registers via Semi-Tensor Product","display_name":"Low-Latency Serial-to-Parallel Conversion for Feedback Shift Registers via Semi-Tensor Product","publication_year":2025,"publication_date":"2025-10-14","ids":{"openalex":"https://openalex.org/W4415968559","doi":"https://doi.org/10.1109/iecon58223.2025.11221130"},"language":null,"primary_location":{"id":"doi:10.1109/iecon58223.2025.11221130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iecon58223.2025.11221130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IECON 2025 \u2013 51st Annual Conference of the IEEE Industrial Electronics Society","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101759190","display_name":"Jianmin Wang","orcid":"https://orcid.org/0000-0003-2427-6979"},"institutions":[{"id":"https://openalex.org/I159389169","display_name":"Ningbo University of Technology","ror":"https://ror.org/037dym702","country_code":"CN","type":"education","lineage":["https://openalex.org/I159389169"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianmin Wang","raw_affiliation_strings":["Ningbo University of Technology,School of Electronics and Information Engineering,Ningbo,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ningbo University of Technology,School of Electronics and Information Engineering,Ningbo,China","institution_ids":["https://openalex.org/I159389169"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091553280","display_name":"Fengqiu Liu","orcid":"https://orcid.org/0000-0002-4063-4337"},"institutions":[{"id":"https://openalex.org/I159389169","display_name":"Ningbo University of Technology","ror":"https://ror.org/037dym702","country_code":"CN","type":"education","lineage":["https://openalex.org/I159389169"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fengqiu Liu","raw_affiliation_strings":["Ningbo University of Technology,School of Statistics and Data Science,Ningbo,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ningbo University of Technology,School of Statistics and Data Science,Ningbo,China","institution_ids":["https://openalex.org/I159389169"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.26558497,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12303","display_name":"Tensor decomposition and applications","score":0.5152000188827515,"subfield":{"id":"https://openalex.org/subfields/2605","display_name":"Computational Mathematics"},"field":{"id":"https://openalex.org/fields/26","display_name":"Mathematics"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12303","display_name":"Tensor decomposition and applications","score":0.5152000188827515,"subfield":{"id":"https://openalex.org/subfields/2605","display_name":"Computational Mathematics"},"field":{"id":"https://openalex.org/fields/26","display_name":"Mathematics"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.13600000739097595,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.08980000019073486,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.6549999713897705},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6290000081062317},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6238999962806702},{"id":"https://openalex.org/keywords/algebraic-number","display_name":"Algebraic number","score":0.618399977684021},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.5889999866485596},{"id":"https://openalex.org/keywords/algebraic-expression","display_name":"Algebraic expression","score":0.5730000138282776},{"id":"https://openalex.org/keywords/expression","display_name":"Expression (computer science)","score":0.512499988079071},{"id":"https://openalex.org/keywords/product-term","display_name":"Product term","score":0.4453999996185303},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4269999861717224},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.42250001430511475}],"concepts":[{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.6549999713897705},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6290000081062317},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6238999962806702},{"id":"https://openalex.org/C9376300","wikidata":"https://www.wikidata.org/wiki/Q168817","display_name":"Algebraic number","level":2,"score":0.618399977684021},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.5889999866485596},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5842000246047974},{"id":"https://openalex.org/C18912844","wikidata":"https://www.wikidata.org/wiki/Q4724001","display_name":"Algebraic expression","level":3,"score":0.5730000138282776},{"id":"https://openalex.org/C90559484","wikidata":"https://www.wikidata.org/wiki/Q778379","display_name":"Expression (computer science)","level":2,"score":0.512499988079071},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4544000029563904},{"id":"https://openalex.org/C9429942","wikidata":"https://www.wikidata.org/wiki/Q1781698","display_name":"Product term","level":5,"score":0.4453999996185303},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4269999861717224},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.42250001430511475},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40389999747276306},{"id":"https://openalex.org/C90673727","wikidata":"https://www.wikidata.org/wiki/Q901718","display_name":"Product (mathematics)","level":2,"score":0.39480000734329224},{"id":"https://openalex.org/C137627569","wikidata":"https://www.wikidata.org/wiki/Q245471","display_name":"Cyclic redundancy check","level":3,"score":0.3813000023365021},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.366100013256073},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3546000123023987},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.34540000557899475},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3287999927997589},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.3269999921321869},{"id":"https://openalex.org/C158465420","wikidata":"https://www.wikidata.org/wiki/Q1979515","display_name":"Boolean expression","level":3,"score":0.32190001010894775},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30730000138282776},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.30219998955726624},{"id":"https://openalex.org/C105285975","wikidata":"https://www.wikidata.org/wiki/Q2719417","display_name":"Canonical normal form","level":2,"score":0.29510000348091125},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.29350000619888306},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.28600001335144043},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.27300000190734863},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C148607811","wikidata":"https://www.wikidata.org/wiki/Q746863","display_name":"Algebraic function","level":3,"score":0.2621999979019165},{"id":"https://openalex.org/C136003732","wikidata":"https://www.wikidata.org/wiki/Q3854337","display_name":"Algebraic operation","level":3,"score":0.25780001282691956},{"id":"https://openalex.org/C120373497","wikidata":"https://www.wikidata.org/wiki/Q1087987","display_name":"Parallel algorithm","level":2,"score":0.2556999921798706},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.25429999828338623},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.25130000710487366}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iecon58223.2025.11221130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iecon58223.2025.11221130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IECON 2025 \u2013 51st Annual Conference of the IEEE Industrial Electronics Society","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1939942640","https://openalex.org/W2013929706","https://openalex.org/W2022785751","https://openalex.org/W2050191402","https://openalex.org/W2102695687","https://openalex.org/W2340667721","https://openalex.org/W2486512961","https://openalex.org/W2524131723","https://openalex.org/W2793121626","https://openalex.org/W2885704460","https://openalex.org/W4214544218","https://openalex.org/W4251988934","https://openalex.org/W4285201410","https://openalex.org/W4293801805","https://openalex.org/W4313159820","https://openalex.org/W4313447262","https://openalex.org/W4401622848"],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,61,88,104,114],"design":[4],"method":[5,131],"for":[6,47],"converting":[7],"serial-input":[8,28,56,116],"feedback":[9],"shift":[10],"registers":[11],"(FSRs)":[12],"into":[13],"parallel":[14],"circuits":[15,71],"using":[16],"the":[17,23,27,37,41,44,48,55,67,77,81,85,125,130],"Semi-Tensor":[18],"Product":[19],"(STP)":[20],"technique.":[21],"First,":[22],"algebraic":[24,45,82],"expression":[25,46,79],"of":[26,40,69,84,129,134],"FSR":[29,57,117],"is":[30,52,96],"derived":[31,53],"via":[32],"STP.":[33],"Then,":[34],"based":[35,93],"on":[36,94,103,113],"parallelization":[38,86],"level":[39],"input":[42],"sequence,":[43],"parallel-input":[49],"conversion":[50],"circuit":[51],"from":[54,80],"expression,":[58],"along":[59],"with":[60],"sufficient":[62],"condition":[63],"to":[64,98],"ensure":[65],"that":[66],"outputs":[68],"both":[70],"are":[72],"equal.":[73],"Furthermore,":[74],"by":[75],"extracting":[76],"logical":[78],"form":[83],"circuit,":[87],"Boolean":[89],"function":[90],"bi-decomposition":[91],"algorithm":[92],"STP":[95],"applied":[97],"facilitate":[99],"efficient":[100],"hardware":[101],"implementation":[102],"field-programmable":[105],"gate":[106],"array":[107],"(FPGA).":[108],"Numerical":[109],"experiments,":[110],"including":[111],"tests":[112],"nonlinear":[115],"and":[118,127],"cyclic":[119],"redundancy":[120],"check":[121],"(CRC)":[122],"validation,":[123],"demonstrate":[124],"effectiveness":[126],"feasibility":[128],"in":[132],"terms":[133],"latency":[135],"reduction.":[136]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-11-06T00:00:00"}