{"id":"https://openalex.org/W2540425408","doi":"https://doi.org/10.1109/idt.2013.6727132","title":"Exploring test opportunities for memory and interconnects in 3D ICs","display_name":"Exploring test opportunities for memory and interconnects in 3D ICs","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2540425408","doi":"https://doi.org/10.1109/idt.2013.6727132","mag":"2540425408"},"language":"en","primary_location":{"id":"doi:10.1109/idt.2013.6727132","is_oa":false,"landing_page_url":"https://doi.org/10.1109/idt.2013.6727132","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th IEEE Design and Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042250419","display_name":"Mottaqiallah Taouil","orcid":"https://orcid.org/0000-0002-9911-4846"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Mottaqiallah Taouil","raw_affiliation_strings":["Faculty of EE, Mathematics and CS, Delft University of Technology, Delft, CD, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Faculty of EE, Mathematics and CS, Delft University of Technology, Delft, CD, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089051890","display_name":"Mihai Lefter","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Mihai Lefter","raw_affiliation_strings":["Faculty of EE, Mathematics and CS, Delft University of Technology, Delft, CD, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Faculty of EE, Mathematics and CS, Delft University of Technology, Delft, CD, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005739146","display_name":"Said Hamdioui","orcid":"https://orcid.org/0000-0002-8961-0387"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Said Hamdioui","raw_affiliation_strings":["Faculty of EE, Mathematics and CS, Delft University of Technology, Delft, CD, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Faculty of EE, Mathematics and CS, Delft University of Technology, Delft, CD, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5042250419"],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":0.9458,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.79965495,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6707913279533386},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5630119442939758},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.531175434589386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4941389858722687},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4458268880844116},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.4443424940109253},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39810317754745483},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3463709354400635},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3158087134361267},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2369292676448822},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.13963568210601807},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11422401666641235},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08335834741592407}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6707913279533386},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5630119442939758},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.531175434589386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4941389858722687},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4458268880844116},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.4443424940109253},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39810317754745483},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3463709354400635},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3158087134361267},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2369292676448822},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.13963568210601807},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11422401666641235},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08335834741592407}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/idt.2013.6727132","is_oa":false,"landing_page_url":"https://doi.org/10.1109/idt.2013.6727132","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th IEEE Design and Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5899999737739563,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1965451131","https://openalex.org/W2023264348","https://openalex.org/W2028504835","https://openalex.org/W2046574526","https://openalex.org/W2051668240","https://openalex.org/W2074256944","https://openalex.org/W2090396476","https://openalex.org/W2095691046","https://openalex.org/W2095790208","https://openalex.org/W2100597370","https://openalex.org/W2103022917","https://openalex.org/W2104500469","https://openalex.org/W2115697688","https://openalex.org/W2116426145","https://openalex.org/W2118445886","https://openalex.org/W2125982897","https://openalex.org/W2132155220","https://openalex.org/W2133279383","https://openalex.org/W2137893918","https://openalex.org/W2143502515","https://openalex.org/W2149593163","https://openalex.org/W2161277442","https://openalex.org/W2163707679","https://openalex.org/W2185926888","https://openalex.org/W2484844306","https://openalex.org/W4205976331","https://openalex.org/W4230995773","https://openalex.org/W4231050950","https://openalex.org/W4239250096","https://openalex.org/W4285719527","https://openalex.org/W4300936028","https://openalex.org/W6677740069"],"related_works":["https://openalex.org/W2016970881","https://openalex.org/W2126420455","https://openalex.org/W1990828594","https://openalex.org/W2333804548","https://openalex.org/W3093450488","https://openalex.org/W2250058922","https://openalex.org/W2027159884","https://openalex.org/W2016589506","https://openalex.org/W3163301441","https://openalex.org/W1522190160"],"abstract_inverted_index":{"3D-Stacked":[0],"IC":[1],"(3D-SIC)":[2],"based":[3],"on":[4,42,114,145,150],"Through-Silicon-Vias":[5],"(TSV)":[6],"is":[7,36,98,133],"an":[8],"emerging":[9],"technology":[10],"that":[11],"provides":[12],"many":[13],"benefits":[14,35,126],"such":[15,34,47],"as":[16,64],"low":[17,85],"power,":[18],"high":[19,88],"bandwidth":[20],"3D":[21],"memories":[22,112,138],"and":[23,87,116,127,141],"heterogeneous":[24],"integration.":[25],"One":[26],"of":[27,33,39,99,107,129],"the":[28,37,71,120,146],"attractive":[29],"applications":[30],"making":[31],"used":[32],"stacking":[38],"memory":[40,80,147],"dies":[41,148],"logic.":[43],"System":[44],"integrators":[45],"for":[46,111,136],"application":[48],"have":[49,57],"to":[50,58,69],"provide":[51],"appropriate":[52],"test":[53,90,109],"strategy.":[54],"However,":[55],"they":[56,75],"deal":[59],"with":[60,140],"block":[61],"box":[62],"IPs":[63],"IP":[65,72],"providers":[66],"usually":[67],"refuse":[68],"share":[70],"content.":[73],"Moreover,":[74],"dislike":[76],"including":[77],"JTAG":[78,123],"in":[79],"dies.":[81],"Therefore,":[82],"developing":[83],"a":[84,105,151],"cost":[86],"quality":[89],"approaches,":[91],"while":[92],"taking":[93],"these":[94],"constraints":[95],"into":[96],"consideration,":[97],"great":[100],"importance.":[101],"This":[102],"paper":[103],"presents":[104],"framework":[106],"interconnect":[108],"approaches":[110],"stacked":[113,137],"logic,":[115],"look":[117],"further":[118],"than":[119],"only":[121],"proposed":[122],"solutions.":[124],"The":[125],"drawbacks":[128],"each":[130],"possible":[131],"solution":[132],"extensively":[134],"discusses":[135],"both":[139],"without":[142],"MBISTs,":[143],"placed":[144],"or":[149],"separate":[152],"logic":[153],"die.":[154]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}