{"id":"https://openalex.org/W2029518208","doi":"https://doi.org/10.1109/idt.2013.6727109","title":"Design space exploration and synthesis for digital signal processing algorithms from Simulink models","display_name":"Design space exploration and synthesis for digital signal processing algorithms from Simulink models","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2029518208","doi":"https://doi.org/10.1109/idt.2013.6727109","mag":"2029518208"},"language":"en","primary_location":{"id":"doi:10.1109/idt.2013.6727109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/idt.2013.6727109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th IEEE Design and Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027243148","display_name":"Shahzad Ahmad Butt","orcid":"https://orcid.org/0000-0002-9747-221X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Shahzad Ahmad Butt","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luciano Lavagno","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5027243148"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.9456,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.75546826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.8153091669082642},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7574094533920288},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7460752129554749},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7312332391738892},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6979950666427612},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5336941480636597},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.48027873039245605},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.4624585807323456},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.44078847765922546},{"id":"https://openalex.org/keywords/model-based-design","display_name":"Model-based design","score":0.43224990367889404},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4320526123046875},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.4198063611984253},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41352203488349915},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4114251434803009},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3919762969017029},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.21066418290138245},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.1796751320362091},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14180299639701843}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.8153091669082642},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7574094533920288},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7460752129554749},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7312332391738892},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6979950666427612},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5336941480636597},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.48027873039245605},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.4624585807323456},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.44078847765922546},{"id":"https://openalex.org/C195672273","wikidata":"https://www.wikidata.org/wiki/Q6888132","display_name":"Model-based design","level":2,"score":0.43224990367889404},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4320526123046875},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.4198063611984253},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41352203488349915},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4114251434803009},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3919762969017029},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.21066418290138245},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.1796751320362091},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14180299639701843},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/idt.2013.6727109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/idt.2013.6727109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th IEEE Design and Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1515932869","https://openalex.org/W1517872072","https://openalex.org/W2046317813","https://openalex.org/W2054608565","https://openalex.org/W2111794983","https://openalex.org/W2119674509","https://openalex.org/W2144248622","https://openalex.org/W2153929699","https://openalex.org/W2161294182","https://openalex.org/W2534518344","https://openalex.org/W2556917441","https://openalex.org/W2751592354","https://openalex.org/W4229943461"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W3146054601","https://openalex.org/W2037960874","https://openalex.org/W2269990635","https://openalex.org/W4285464654","https://openalex.org/W3013057549","https://openalex.org/W2906427691","https://openalex.org/W2507786429","https://openalex.org/W2139127070"],"abstract_inverted_index":{"Design":[0],"teams":[1],"are":[2],"increasingly":[3],"looking":[4],"for":[5,62,89,123],"design":[6,23,60,68,121,128,149],"flows":[7],"that":[8,137],"can":[9,24,103],"rapidly":[10],"lead":[11],"to":[12,41,50],"high":[13,64],"performance":[14],"and":[15,47,114,126],"low":[16],"power":[17],"implementation":[18,136,143],"of":[19,45,93,95],"DSP":[20],"algorithms.":[21],"Model-based":[22],"satisfy":[25],"this":[26],"requirement,":[27],"but":[28],"it":[29],"must":[30],"be":[31],"(1)":[32],"coupled":[33],"with":[34,82,140],"efficient":[35,134],"high-level":[36],"synthesis":[37,125],"support":[38],"in":[39,112],"order":[40],"provide":[42],"good":[43],"Quality":[44],"Results,":[46],"(2)":[48],"controlled":[49],"derive":[51],"the":[52,91,141],"desired":[53],"area/performance/throughput":[54],"trade-off.":[55],"We":[56,78,99],"present":[57],"a":[58,83,96,106,118,132],"semi-automatic":[59],"flow":[61,81,122],"rapid":[63],"level":[65],"synthesis-based":[66],"hardware":[67,124,135],"space":[69,129],"exploration":[70],"starting":[71],"from":[72,105],"Simulink":[73,113],"digital":[74],"signal":[75,86],"processing":[76,87],"models.":[77],"illustrate":[79],"our":[80],"realistically":[84],"complex":[85],"algorithm":[88],"estimating":[90],"direction":[92],"arrival":[94],"sound":[97],"source.":[98],"show":[100],"how":[101],"one":[102],"start":[104],"functionally":[107],"validated":[108],"fixed":[109],"point":[110],"model":[111],"then":[115],"go":[116],"through":[117],"relatively":[119],"simple":[120],"automatic":[127],"exploration,":[130],"obtaining":[131],"very":[133],"is":[138],"competitive":[139],"RTL":[142],"generated":[144],"by":[145],"another":[146],"commercial":[147],"model-based":[148],"tool.":[150]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}