{"id":"https://openalex.org/W2545310974","doi":"https://doi.org/10.1109/idt.2010.5724404","title":"Design and implementation of low latency network interface for network on chip","display_name":"Design and implementation of low latency network interface for network on chip","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W2545310974","doi":"https://doi.org/10.1109/idt.2010.5724404","mag":"2545310974"},"language":"en","primary_location":{"id":"doi:10.1109/idt.2010.5724404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/idt.2010.5724404","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 5th International Design and Test Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054816920","display_name":"Brahim Attia","orcid":null},"institutions":[{"id":"https://openalex.org/I166928557","display_name":"University of Monastir","ror":"https://ror.org/00nhtcg76","country_code":"TN","type":"education","lineage":["https://openalex.org/I166928557"]}],"countries":["TN"],"is_corresponding":true,"raw_author_name":"Brahim Attia","raw_affiliation_strings":["Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia"],"affiliations":[{"raw_affiliation_string":"Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia","institution_ids":["https://openalex.org/I166928557"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087811645","display_name":"Wissem Chouchene","orcid":null},"institutions":[{"id":"https://openalex.org/I166928557","display_name":"University of Monastir","ror":"https://ror.org/00nhtcg76","country_code":"TN","type":"education","lineage":["https://openalex.org/I166928557"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Wissem Chouchene","raw_affiliation_strings":["Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia"],"affiliations":[{"raw_affiliation_string":"Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia","institution_ids":["https://openalex.org/I166928557"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011463917","display_name":"Abdelkrim Zitouni","orcid":"https://orcid.org/0000-0001-7604-2694"},"institutions":[{"id":"https://openalex.org/I166928557","display_name":"University of Monastir","ror":"https://ror.org/00nhtcg76","country_code":"TN","type":"education","lineage":["https://openalex.org/I166928557"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Abdelkrim Zitouni","raw_affiliation_strings":["Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia"],"affiliations":[{"raw_affiliation_string":"Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia","institution_ids":["https://openalex.org/I166928557"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068287463","display_name":"Abid Nourdin","orcid":null},"institutions":[{"id":"https://openalex.org/I166928557","display_name":"University of Monastir","ror":"https://ror.org/00nhtcg76","country_code":"TN","type":"education","lineage":["https://openalex.org/I166928557"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Abid Nourdin","raw_affiliation_strings":["Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia"],"affiliations":[{"raw_affiliation_string":"Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia","institution_ids":["https://openalex.org/I166928557"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113788610","display_name":"Rached Tourki","orcid":null},"institutions":[{"id":"https://openalex.org/I166928557","display_name":"University of Monastir","ror":"https://ror.org/00nhtcg76","country_code":"TN","type":"education","lineage":["https://openalex.org/I166928557"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Rached Tourki","raw_affiliation_strings":["Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia"],"affiliations":[{"raw_affiliation_string":"Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME), Monastir, Tunisia","institution_ids":["https://openalex.org/I166928557"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5054816920"],"corresponding_institution_ids":["https://openalex.org/I166928557"],"apc_list":null,"apc_paid":null,"fwci":2.1367,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.88854878,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"42"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.987500011920929,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.7208045125007629},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7108423709869385},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.7012613415718079},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.663119912147522},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6570209264755249},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5888692736625671},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5775709748268127},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5132195949554443},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4942205250263214},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.4831642508506775},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4657398462295532},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3382588028907776},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20900940895080566}],"concepts":[{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.7208045125007629},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7108423709869385},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.7012613415718079},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.663119912147522},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6570209264755249},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5888692736625671},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5775709748268127},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5132195949554443},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4942205250263214},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.4831642508506775},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4657398462295532},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3382588028907776},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20900940895080566},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/idt.2010.5724404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/idt.2010.5724404","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 5th International Design and Test Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1546907442","https://openalex.org/W1548385402","https://openalex.org/W1600358781","https://openalex.org/W1969899927","https://openalex.org/W2015228774","https://openalex.org/W2080527951","https://openalex.org/W2104674486","https://openalex.org/W2113800828","https://openalex.org/W2119677480","https://openalex.org/W2126213936","https://openalex.org/W2147199237","https://openalex.org/W2151415616","https://openalex.org/W2151888078","https://openalex.org/W2159522462","https://openalex.org/W2160642395","https://openalex.org/W2168930811","https://openalex.org/W2170792664","https://openalex.org/W2462193902","https://openalex.org/W2538960833","https://openalex.org/W3143338891","https://openalex.org/W4233551234","https://openalex.org/W4255289115","https://openalex.org/W4309981097","https://openalex.org/W7073707567"],"related_works":["https://openalex.org/W2382274995","https://openalex.org/W2371307874","https://openalex.org/W2052816277","https://openalex.org/W2167988973","https://openalex.org/W2603824091","https://openalex.org/W2439487276","https://openalex.org/W2560886726","https://openalex.org/W2091258882","https://openalex.org/W2541438272","https://openalex.org/W2013729863"],"abstract_inverted_index":{"The":[0],"implementation":[1],"of":[2,11,41,147],"a":[3,31,141],"high-performance":[4],"network-on-chip":[5],"(NoC)":[6],"requires":[7],"an":[8],"efficient":[9,135],"design":[10],"the":[12,19,23,75,98,103,128],"network":[13,21,44],"interface":[14],"(NI)":[15],"unit":[16],"that":[17,127],"connects":[18],"switched":[20],"to":[22,49,54,73,80],"IP":[24,76,99],"cores.":[25],"In":[26],"this":[27,89],"paper,":[28],"we":[29,65,91],"present":[30,63],"two":[32],"novel":[33],"pipelined":[34],"NI":[35,112],"architecture":[36],"between":[37,69],"IPs":[38,53,95],"and":[39,56,71,78,101,117,134,136,152],"router":[40],"NOC.":[42],"These":[43],"interfaces":[45],"allow":[46],"system":[47],"designers":[48],"send":[50],"data":[51],"from":[52,84],"NOC,":[55],"vice":[57],"versa":[58],"with":[59],"low":[60],"latency.":[61],"We":[62],"how":[64],"can":[66],"apply":[67],"decoupling":[68],"computation":[70],"communications":[72],"achieve":[74],"modules":[77],"interconnections":[79],"be":[81],"designed":[82],"independently":[83],"each":[85],"other.":[86],"To":[87],"validate":[88],"approach,":[90],"use":[92,102],"AMBA":[93],"AHB":[94],"standard":[96],"at":[97],"side":[100],"most":[104],"three":[105],"used":[106],"flow":[107],"control":[108],"in":[109,115,145],"NoC.":[110],"This":[111],"was":[113],"modeled":[114],"VHDL":[116],"implemented":[118],"on":[119],"Xilinx":[120],"Virtex5":[121],"FPGA":[122],"board.":[123],"Experimental":[124],"results":[125],"show":[126],"proposed":[129],"Network":[130],"Interfaces":[131],"is":[132,138],"feasible":[133],"it":[137],"characterized":[139],"by":[140],"good":[142],"performance":[143],"criteria's":[144],"terms":[146],"area,":[148],"power,":[149],"speed,":[150],"latency,":[151],"Throughput.":[153]},"counts_by_year":[{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}