{"id":"https://openalex.org/W2131465271","doi":"https://doi.org/10.1109/icvd.2004.1261041","title":"Digital design: the components of a new paradigm","display_name":"Digital design: the components of a new paradigm","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2131465271","doi":"https://doi.org/10.1109/icvd.2004.1261041","mag":"2131465271"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1261041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009840867","display_name":"Rashmi Gupta","orcid":"https://orcid.org/0000-0003-0046-6700"},"institutions":[{"id":"https://openalex.org/I76610242","display_name":"Cypress Semiconductor Corporation (Japan)","ror":"https://ror.org/0561ky130","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210127281","https://openalex.org/I76610242"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"R. Gupta","raw_affiliation_strings":["Cypress Semiconductor, Bangalore, India","Cypress Semiconductor, Bangalore India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cypress Semiconductor, Bangalore, India","institution_ids":[]},{"raw_affiliation_string":"Cypress Semiconductor, Bangalore India","institution_ids":["https://openalex.org/I76610242"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5009840867"],"corresponding_institution_ids":["https://openalex.org/I76610242"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"877","last_page":"880"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.9208953380584717},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7496646642684937},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5791354179382324},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5345112085342407},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5096790790557861},{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.4730711877346039},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46197783946990967},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4497147798538208},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.42300453782081604},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42228826880455017},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4179503917694092},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3968481421470642},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33953243494033813},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.33362680673599243},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3292032480239868},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16815504431724548},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11932599544525146}],"concepts":[{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.9208953380584717},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7496646642684937},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5791354179382324},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5345112085342407},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5096790790557861},{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.4730711877346039},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46197783946990967},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4497147798538208},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.42300453782081604},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42228826880455017},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4179503917694092},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3968481421470642},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33953243494033813},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.33362680673599243},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3292032480239868},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16815504431724548},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11932599544525146},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1261041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1550038530","https://openalex.org/W1609287256","https://openalex.org/W1620963342","https://openalex.org/W1995779373","https://openalex.org/W2008833281","https://openalex.org/W2102160092","https://openalex.org/W2106315327","https://openalex.org/W2109678242","https://openalex.org/W2114567137","https://openalex.org/W2133717905","https://openalex.org/W2564921634","https://openalex.org/W2567262142","https://openalex.org/W2894705485","https://openalex.org/W4300297211","https://openalex.org/W6721165358"],"related_works":["https://openalex.org/W1929041301","https://openalex.org/W2038859986","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W4230312832","https://openalex.org/W1982273910","https://openalex.org/W2032882110","https://openalex.org/W2127843031","https://openalex.org/W2125423773","https://openalex.org/W2536819812"],"abstract_inverted_index":{"The":[0],"digital":[1],"design":[2],"paradigm":[3],"is":[4],"in":[5,35],"transition.":[6],"We":[7,39,55],"discuss":[8],"on-chip":[9],"programmable":[10],"regulators":[11],"to":[12,18,32,41,57,61,70],"reduce":[13,19,71],"power":[14],"consumption;":[15],"SERDES":[16],"blocks":[17],"the":[20,63,72],"inter-block":[21],"interconnections":[22],"and":[23,30,44,67],"small":[24],"signal":[25],"swing":[26],"high-speed":[27],"differential":[28],"inputs":[29],"outputs":[31],"maximize":[33],"performance":[34],"interconnect":[36],"delay-dominated":[37],"technologies.":[38],"need":[40,56],"build":[42],"re-configurability":[43],"re-use":[45],"of":[46,52,74],"logic":[47],"as":[48],"an":[49],"essential":[50],"feature":[51],"device":[53],"functionality.":[54],"adopt":[58],"self-calibration":[59],"mechanisms":[60],"solve":[62],"timing":[64],"closure":[65],"problem":[66],"find":[68],"ways":[69],"cost":[73],"test":[75],"by":[76],"design.":[77]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
