{"id":"https://openalex.org/W2169510384","doi":"https://doi.org/10.1109/icvd.2004.1261040","title":"Estimating pre-placement FPGA interconnection requirements","display_name":"Estimating pre-placement FPGA interconnection requirements","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2169510384","doi":"https://doi.org/10.1109/icvd.2004.1261040","mag":"2169510384"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1261040","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112222457","display_name":"Parivallal Kannan","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Kannan","raw_affiliation_strings":["Center for Integrated Circuits and Systems, Erik Jonsson, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems, Erik Jonsson, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069692759","display_name":"Dinesh Bhatia","orcid":"https://orcid.org/0000-0002-5019-7417"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Bhatia","raw_affiliation_strings":["Center for Integrated Circuits and Systems, Erik Jonsson, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems, Erik Jonsson, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112222457"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.9875,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.78588822,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"21","issue":null,"first_page":"869","last_page":"874"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9430961012840271},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7742490768432617},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.7614870071411133},{"id":"https://openalex.org/keywords/minimum-bounding-box","display_name":"Minimum bounding box","score":0.7260528206825256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6859011650085449},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6813703179359436},{"id":"https://openalex.org/keywords/bounding-overwatch","display_name":"Bounding overwatch","score":0.6731102466583252},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6499547362327576},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.647524893283844},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5855205655097961},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5614386200904846},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.4634895324707031},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.443956583738327},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.42638155817985535},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4127654433250427},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.40035322308540344},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27459824085235596},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.23237240314483643},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11327356100082397}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9430961012840271},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7742490768432617},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.7614870071411133},{"id":"https://openalex.org/C147037132","wikidata":"https://www.wikidata.org/wiki/Q6865426","display_name":"Minimum bounding box","level":3,"score":0.7260528206825256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6859011650085449},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6813703179359436},{"id":"https://openalex.org/C63584917","wikidata":"https://www.wikidata.org/wiki/Q333286","display_name":"Bounding overwatch","level":2,"score":0.6731102466583252},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6499547362327576},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.647524893283844},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5855205655097961},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5614386200904846},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.4634895324707031},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.443956583738327},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.42638155817985535},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4127654433250427},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40035322308540344},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27459824085235596},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.23237240314483643},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11327356100082397},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1261040","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W6504023","https://openalex.org/W1556480701","https://openalex.org/W1597088765","https://openalex.org/W1968581024","https://openalex.org/W1970970490","https://openalex.org/W1978599303","https://openalex.org/W1980746862","https://openalex.org/W1989060364","https://openalex.org/W1991530123","https://openalex.org/W2015540924","https://openalex.org/W2017843246","https://openalex.org/W2020112047","https://openalex.org/W2024060531","https://openalex.org/W2029853052","https://openalex.org/W2056883404","https://openalex.org/W2085374061","https://openalex.org/W2095117703","https://openalex.org/W2111104699","https://openalex.org/W2112547226","https://openalex.org/W2135336405","https://openalex.org/W2139637699","https://openalex.org/W2148219318","https://openalex.org/W2161455936","https://openalex.org/W2162908425","https://openalex.org/W4236269389","https://openalex.org/W4247132266","https://openalex.org/W4285719527","https://openalex.org/W6600255923","https://openalex.org/W6642358715","https://openalex.org/W6674354551","https://openalex.org/W6676477664","https://openalex.org/W6677586052","https://openalex.org/W6680692090"],"related_works":["https://openalex.org/W2350308400","https://openalex.org/W2064910292","https://openalex.org/W1987487129","https://openalex.org/W2030503305","https://openalex.org/W2164654367","https://openalex.org/W1557016741","https://openalex.org/W151789180","https://openalex.org/W3197841175","https://openalex.org/W2082193796","https://openalex.org/W2077246255"],"abstract_inverted_index":{"With":[0],"increasing":[1],"device":[2],"and":[3,73,111,148,156],"design":[4,13,37,67],"sizes,":[5],"Interconnect":[6],"Planning":[7],"is":[8,26,62],"fast":[9],"becoming":[10],"an":[11,103],"important":[12],"issue":[14],"for":[15,23,65],"large":[16],"FPGA":[17,165],"based":[18,85],"designs.":[19,142],"The":[20],"fundamental":[21],"requirement":[22],"interconnect":[24,47],"planning":[25],"the":[27,31,89,113,118,123,128,134,154],"ability":[28],"to":[29,58,87,99,108,126],"estimate":[30,88,112],"routing":[32],"requirements":[33],"of":[34,41,46,76,91,116,133],"a":[35,80,95,162],"given":[36,96],"at":[38],"all":[39,117],"stages":[40,75],"physical":[42],"design.":[43,77],"A":[44],"number":[45],"estimation":[48,61],"methods":[49],"have":[50],"been":[51],"proposed,":[52],"but":[53],"very":[54,63],"few":[55],"operate":[56],"prior":[57,98],"placement.":[59,100],"Pre-placement":[60],"useful":[64],"detailed":[66],"space":[68],"exploration":[69],"during":[70],"logic":[71],"synthesis":[72],"earlier":[74],"We":[78,101,120,143],"propose":[79],"new":[81],"local":[82],"neighborhood":[83],"analysis":[84],"method":[86,137],"wirelengths":[90],"every":[92],"net":[93,146],"in":[94],"netlist,":[97],"assume":[102],"optimal":[104],"placement":[105],"with":[106,153],"respect":[107],"total":[109],"wirelength":[110],"bounding-box":[114,124,147],"sizes":[115],"nets.":[119],"then":[121],"use":[122],"estimates":[125,152],"compute":[127],"post-routing":[129,157],"peak":[130,149],"channel":[131,150],"width":[132,151],"device.":[135],"Our":[136],"efficiently":[138],"handles":[139],"pad":[140],"constrained":[141],"compare":[144],"our":[145],"post-placement":[155],"results":[158],"obtained":[159],"using":[160],"VPR,":[161],"commonly":[163],"used":[164],"tool":[166],"suite.":[167]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}