{"id":"https://openalex.org/W2151887706","doi":"https://doi.org/10.1109/icvd.2004.1261029","title":"Reset careabouts in a SoC design","display_name":"Reset careabouts in a SoC design","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2151887706","doi":"https://doi.org/10.1109/icvd.2004.1261029","mag":"2151887706"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1261029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000276780","display_name":"Subrangshu Das","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Das","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111626552","display_name":"S. Chandar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Chandar","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102801690","display_name":"Ashish Tiwari","orcid":"https://orcid.org/0000-0002-1441-1797"},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Tiwari","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210109535"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.18106393,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"788","last_page":"791"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.94627845287323},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7124844789505005},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6696922779083252},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5983277559280396},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4994654655456543},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4799249768257141},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.45873916149139404},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4513331353664398},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4444340765476227},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42975515127182007},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39019057154655457},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32059213519096375},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21712151169776917},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13254788517951965}],"concepts":[{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.94627845287323},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7124844789505005},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6696922779083252},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5983277559280396},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4994654655456543},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4799249768257141},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.45873916149139404},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4513331353664398},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4444340765476227},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42975515127182007},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39019057154655457},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32059213519096375},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21712151169776917},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13254788517951965},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1261029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2168404746","https://openalex.org/W6684852646"],"related_works":["https://openalex.org/W4244547561","https://openalex.org/W1929041301","https://openalex.org/W2038859986","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W4230312832","https://openalex.org/W1982273910","https://openalex.org/W2032882110","https://openalex.org/W2127843031","https://openalex.org/W2125423773"],"abstract_inverted_index":{"Advances":[0],"in":[1,11],"VLSI":[2],"technology":[3],"have":[4],"enabled":[5],"designers":[6],"to":[7,53,81],"integrate":[8],"more":[9],"functionality":[10],"one":[12],"chip.":[13],"One":[14],"of":[15],"the":[16,25,82,86],"major":[17],"design":[18],"complexities":[19],"arising":[20],"from":[21],"this":[22,58],"is":[23],"defining":[24],"reset":[26,83,87],"architecture":[27],"for":[28],"a":[29,54],"SoC,":[30],"especially":[31],"when":[32],"there":[33],"are":[34,89],"multiple":[35],"clock":[36],"domains.":[37],"Incorrect":[38],"assumptions":[39],"or":[40,50],"overlooked":[41],"issues":[42],"might":[43],"cause":[44],"silicon":[45,67],"bugs":[46],"requiring":[47],"costly":[48],"re-spins":[49],"even":[51],"worse":[52],"missed":[55],"opportunity.":[56],"In":[57],"paper,":[59],"various":[60],"careabouts":[61],"that":[62],"help":[63],"achieve":[64],"first":[65],"pass":[66],"success":[68],"as":[69,71],"well":[70],"reduced":[72],"verification":[73],"and":[74,85],"manufacturing":[75],"test":[76],"generation":[77],"effort":[78],"with":[79],"respect":[80],"signal":[84],"state":[88],"described.":[90]},"counts_by_year":[{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}