{"id":"https://openalex.org/W2160130484","doi":"https://doi.org/10.1109/icvd.2004.1261028","title":"Enhancing SAT-based Bounded Model Checking using sequential logic implications","display_name":"Enhancing SAT-based Bounded Model Checking using sequential logic implications","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2160130484","doi":"https://doi.org/10.1109/icvd.2004.1261028","mag":"2160130484"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1261028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101598230","display_name":"Rajat Arora","orcid":"https://orcid.org/0000-0002-0491-8092"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Arora","raw_affiliation_strings":["Electrical and Computer Engineering Department, Virginia Technology, Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108516165","display_name":"Michael S. Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.S. Hsiao","raw_affiliation_strings":["Electrical and Computer Engineering Department, Virginia Technology, Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1249","issue":null,"first_page":"784","last_page":"787"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12423","display_name":"Software Reliability and Analysis Research","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7401936054229736},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5815871357917786},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.5778003931045532},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.537025511264801},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.5305493474006653},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5055944919586182},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.49686720967292786},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.47092384099960327},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.45260491967201233},{"id":"https://openalex.org/keywords/preprocessor","display_name":"Preprocessor","score":0.4449827969074249},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4419912099838257},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.4412238895893097},{"id":"https://openalex.org/keywords/literal","display_name":"Literal (mathematical logic)","score":0.43061119318008423},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.42669248580932617},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4248349070549011},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3860093951225281},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.30987823009490967},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.24162444472312927},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18020811676979065}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7401936054229736},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5815871357917786},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.5778003931045532},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.537025511264801},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.5305493474006653},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5055944919586182},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.49686720967292786},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.47092384099960327},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.45260491967201233},{"id":"https://openalex.org/C34736171","wikidata":"https://www.wikidata.org/wiki/Q918333","display_name":"Preprocessor","level":2,"score":0.4449827969074249},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4419912099838257},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.4412238895893097},{"id":"https://openalex.org/C2780882242","wikidata":"https://www.wikidata.org/wiki/Q14235582","display_name":"Literal (mathematical logic)","level":2,"score":0.43061119318008423},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.42669248580932617},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4248349070549011},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3860093951225281},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.30987823009490967},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24162444472312927},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18020811676979065},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2004.1261028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1555280138","https://openalex.org/W2024148935","https://openalex.org/W2044560939","https://openalex.org/W2061438988","https://openalex.org/W2075959177","https://openalex.org/W2114725357","https://openalex.org/W2115780004","https://openalex.org/W2117189826","https://openalex.org/W2142785340","https://openalex.org/W2145117664","https://openalex.org/W2160667400","https://openalex.org/W2162116017","https://openalex.org/W2167452021","https://openalex.org/W2168081446","https://openalex.org/W2340735175","https://openalex.org/W2913459036","https://openalex.org/W3045969830","https://openalex.org/W4205536549","https://openalex.org/W4241233758","https://openalex.org/W4253970047","https://openalex.org/W4300021588","https://openalex.org/W6677252870","https://openalex.org/W6781487302"],"related_works":["https://openalex.org/W4295885746","https://openalex.org/W1993361087","https://openalex.org/W2077988164","https://openalex.org/W1589254173","https://openalex.org/W2938781954","https://openalex.org/W1579329129","https://openalex.org/W2133001125","https://openalex.org/W1499470128","https://openalex.org/W4299734787","https://openalex.org/W1483234894"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,37],"novel":[3],"technique":[4],"of":[5,26,40,82,105],"improving":[6],"the":[7,22,27,34,63,70,78,89,94,123],"SAT-based":[8],"Bounded":[9],"Model":[10],"Checking,":[11],"by":[12],"inducing":[13],"powerful":[14],"sequential":[15,44,65],"signal":[16],"correlations":[17],"(crossing":[18],"time-frame":[19],"boundaries)":[20],"into":[21,54],"original":[23],"CNF":[24,72],"formula":[25],"unrolled":[28,64],"circuit.":[29],"A":[30],"quick":[31],"preprocessing":[32],"on":[33,109],"circuit-under-verification,":[35],"builds":[36],"large":[38],"set":[39],"direct":[41],"and":[42,67,85],"indirect":[43],"implications.":[45],"The":[46,74],"non-trivial":[47],"implications":[48],"(spanning":[49],"multiple":[50],"time-frames)":[51],"are":[52,59],"converted":[53],"two-literal":[55],"clauses.":[56],"These":[57],"clauses":[58,76],"quickly":[60],"replicated":[61],"throughout":[62],"circuit,":[66],"appended":[68],"to":[69],"existing":[71],"database.":[73],"added":[75],"prune":[77],"overall":[79],"search":[80],"space":[81],"SAT-solver":[83],"engine":[84],"provide":[86],"correlation":[87],"among":[88],"different":[90],"variables,":[91],"which":[92],"enhances":[93],"Boolean":[95],"Constraint":[96],"Propagation":[97],"(BCP).":[98],"Experimental":[99],"Results":[100],"for":[101],"checking":[102],"difficult":[103],"instances":[104],"random":[106],"safety":[107],"properties":[108],"ISCAS'89":[110],"benchmark":[111],"circuits":[112],"show":[113],"that":[114],"more":[115],"than":[116],"148x":[117],"speedup":[118],"can":[119],"be":[120],"achieved":[121],"over":[122],"conventional":[124],"approach.":[125]},"counts_by_year":[{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}