{"id":"https://openalex.org/W2153559035","doi":"https://doi.org/10.1109/icvd.2004.1261027","title":"Synthesis of application specific multiprocessor architectures for process networks","display_name":"Synthesis of application specific multiprocessor architectures for process networks","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2153559035","doi":"https://doi.org/10.1109/icvd.2004.1261027","mag":"2153559035"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2004.1261027","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261027","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011346326","display_name":"B.K. Dwivedi","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B.K. Dwivedi","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101478917","display_name":"Anshul Kumar","orcid":"https://orcid.org/0000-0002-3871-5402"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Kumar","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102857440","display_name":"S. Balakrishnan","orcid":"https://orcid.org/0009-0000-2568-0151"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Balakrishnan","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I68891433"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"780","last_page":"783"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8289146423339844},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.746112585067749},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6339840888977051},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5873246788978577},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5452668070793152},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4849405586719513},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4659596085548401},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43404263257980347},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17698243260383606}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8289146423339844},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.746112585067749},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6339840888977051},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5873246788978577},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5452668070793152},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4849405586719513},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4659596085548401},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43404263257980347},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17698243260383606},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icvd.2004.1261027","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2004.1261027","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th International Conference on VLSI Design. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.58.395","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.58.395","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.iitd.ernet.in/esproject/homepage/docs/pubs/basant_vlsi04.ps.gz","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":60,"referenced_works":["https://openalex.org/W129392720","https://openalex.org/W206155649","https://openalex.org/W1520460310","https://openalex.org/W1540522725","https://openalex.org/W1556885469","https://openalex.org/W1582450315","https://openalex.org/W1597755753","https://openalex.org/W1804921254","https://openalex.org/W1850405760","https://openalex.org/W1908933176","https://openalex.org/W1937002962","https://openalex.org/W1975990410","https://openalex.org/W1976459683","https://openalex.org/W1976936212","https://openalex.org/W1996109622","https://openalex.org/W2014497214","https://openalex.org/W2040466547","https://openalex.org/W2042921956","https://openalex.org/W2047390207","https://openalex.org/W2059343142","https://openalex.org/W2060200080","https://openalex.org/W2060259574","https://openalex.org/W2067125172","https://openalex.org/W2080527951","https://openalex.org/W2094708468","https://openalex.org/W2094920868","https://openalex.org/W2095668603","https://openalex.org/W2102387714","https://openalex.org/W2106138852","https://openalex.org/W2113532306","https://openalex.org/W2114732989","https://openalex.org/W2114758860","https://openalex.org/W2117285153","https://openalex.org/W2121817468","https://openalex.org/W2127044011","https://openalex.org/W2128075961","https://openalex.org/W2128928505","https://openalex.org/W2130484824","https://openalex.org/W2132678462","https://openalex.org/W2134684843","https://openalex.org/W2138612658","https://openalex.org/W2138625816","https://openalex.org/W2149236729","https://openalex.org/W2150090886","https://openalex.org/W2150408604","https://openalex.org/W2150761058","https://openalex.org/W2153559035","https://openalex.org/W2157554125","https://openalex.org/W2158327022","https://openalex.org/W2160737725","https://openalex.org/W2161191766","https://openalex.org/W2166720067","https://openalex.org/W2172252595","https://openalex.org/W2484908051","https://openalex.org/W4235470811","https://openalex.org/W4249006057","https://openalex.org/W4285719527","https://openalex.org/W6605256877","https://openalex.org/W6635964534","https://openalex.org/W6682791290"],"related_works":["https://openalex.org/W1980880150","https://openalex.org/W325986762","https://openalex.org/W2092845486","https://openalex.org/W1809394610","https://openalex.org/W2123607806","https://openalex.org/W2159088946","https://openalex.org/W2509294597","https://openalex.org/W4237297230","https://openalex.org/W1512205084","https://openalex.org/W1487480684"],"abstract_inverted_index":{"In":[0,119],"this":[1],"paper,":[2],"we":[3,123],"address":[4],"the":[5,32,36,74,79,91,117],"problem":[6],"of":[7,9,18,44,53,55,78,82,95,105,112],"synthesis":[8,40,132],"application":[10,22,37],"specific":[11],"multiprocessor":[12],"SoC":[13],"architectures":[14],"for":[15],"process":[16,41],"networks":[17],"streaming":[19],"applications.":[20],"An":[21],"is":[23,85,133],"modeled":[24],"as":[25],"Kahn":[26],"Process":[27],"Network":[28],"(KPN)":[29],"which":[30],"makes":[31],"parallelism":[33],"present":[34],"in":[35],"explicit.":[38],"The":[39],"involves":[42],"selection":[43],"computation":[45],"modules,":[46,48],"memory":[47,63],"communication":[49,97],"architecture":[50],"and":[51,60,114,131],"mapping":[52,130],"processes":[54,113],"KPN":[56,106],"on":[57,62],"compute":[58],"units":[59],"channels":[61],"modules.":[64],"Our":[65,99],"solution":[66],"minimizes":[67],"hardware":[68],"cost":[69],"while":[70],"taking":[71],"into":[72,89],"account":[73,90],"performance":[75],"constraints.":[76],"One":[77],"salient":[80],"features":[81],"our":[83],"work":[84],"that":[86],"it":[87],"takes":[88],"additional":[92],"overheads":[93],"because":[94],"data":[96,109],"conflicts.":[98],"method":[100],"uses":[101],"average":[102],"processing":[103],"requirements":[104],"to":[107,121],"handle":[108],"dependent":[110],"behavior":[111],"cycles":[115],"within":[116],"KPN.":[118],"contrast":[120],"others,":[122],"do":[124],"not":[125],"perform":[126],"static":[127],"scheduling,":[128],"only":[129],"done.":[134]},"counts_by_year":[{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}